Table of Contents
Low Density Parity Check
Matthew Chaudhuri - CE BS/MS - Encoder and Decoder
Gregory Gluszek - CE BS/MS - GUI and Testbench Design
Bennet Tillapaugh - CE BS/MS - Analysis and Communications Design
Dr. Pratapa Reddy - Faculty Advisor
Dr. Marcin Lukowiak - Faculty Technical Advisor
Dave Coumou - LDPC Technical Advisor
Scott Reardon/D3 Engineering - Sponsor
The proposed project is part of a concatenated coding scheme D3 Engineering is developing for an internally driven project. The outer code of this concatenated coding scheme is performed by a q-ary Low-density Parity-check (LDPC). An initial implementation on a programmable DSP concludes the sequential execution of the decoder is inefficient to attain a suitable data rate and can be ameliorated by a parallel implementation. The fabric of commercially available FPGAs offers the internal memory resources and multipliers for parallel execution. We expect an appropriate FPGA implementation will boast a dramatic performance improvement while freeing DSP resources for other sequentially ordered tasks. To support future instantiations of the q-ary LDPC, we identify a GUI development that will produce the corresponding LDPC encoder and decoder given the generator and parity check matrices and generalized parameters regarding the LDPC implementation and the resources of the target device.
- More information regarding this project can be found on the Project Readiness Package Page
Low-density parity-checking is an error correcting code used for robust communications, originally developed in 1960 by Robert G. Gallager.
GUI - a GUI that can take user input such as LDPC matrix
size and produce all coded needs to create the LDPC
system on an FPGA
Test Platform - a test platform that can test to make sure the LDPC system is working correctly.
- Encoder/Decoder Bit rate must equal or exceed
105 bits per second.
- Bit Error Rate of the system must be less then
10-4 at a SNR of 7 dB.
- Must work with 1/2 to 1/4 code rates.
- Symbol widths must range from 1 to 4 bits.
- Symbol size must be able to range form 4 to 128
- The Encoder and Decoder must work on an FPGA.
- Code must be generated from a GUI.
The final product is a test platform in which random messages are encoded, passed through a noisy channel model and finally decoded. This test platform evaluates the LDPC System and gathers statistics on its performance capabilities.
Concept selection was also performed at this phase of the project. It was an analysis of the trade-offs between different choices that could be made in the design.
We outlined potetential risks and steps we could take to mitigate them.
Our design phase included many revisions of block diagrams presented to the customer during our Design Reviews.
Bit Error RateThe bit error rate required for the LDPC system was 10-4 at a SNR of 7 dB. Our system meets this requirement for all tested cases.
Decoder Bit RateThe decoder bit rate required for the LDPC system was 105. The 1/2 rate decoders meet this requirement at 11 dB. The 1/4 rate decoder does not meet this requirement due to the lower code rate and because the decoder is not fully optimized for the binary case.
Encoder Bit RateThe encoder bit rate required for the LDPC system was 105. All test cases passed this requirement.
The results were gathered in accordance with the test plans developed early in the project design phases.
- Fix issue preventing correct decoding of 1/4 rate
- Optimize the the binary case
- Create faster divider