P08321: Low Density Parity Checking
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Low Density Parity Check

Team Members

Matthew Chaudhuri - CE BS/MS - Encoder and Decoder Design
Gregory Gluszek - CE BS/MS - GUI and Testbench Design
Bennet Tillapaugh - CE BS/MS - Analysis and Communications Design

Dr. Pratapa Reddy - Faculty Advisor
Dr. Marcin Lukowiak - Faculty Technical Advisor
Dave Coumou - LDPC Technical Advisor
Scott Reardon/D3 Engineering - Sponsor

Roles and Responsibilites Matrix

Project Overview

The proposed project is part of a concatenated coding scheme D3 Engineering is developing for an internally driven project. The outer code of this concatenated coding scheme is performed by a q-ary Low-density Parity-check (LDPC). An initial implementation on a programmable DSP concludes the sequential execution of the decoder is inefficient to attain a suitable data rate and can be ameliorated by a parallel implementation. The fabric of commercially available FPGAs offers the internal memory resources and multipliers for parallel execution. We expect an appropriate FPGA implementation will boast a dramatic performance improvement while freeing DSP resources for other sequentially ordered tasks. To support future instantiations of the q-ary LDPC, we identify a GUI development that will produce the corresponding LDPC encoder and decoder given the generator and parity check matrices and generalized parameters regarding the LDPC implementation and the resources of the target device.

FPGA daughtercard on DSP

FPGA daughtercard on DSP

More information regarding this project can be found on the Project Readiness Package Page

One Page Project Summary

LDPC Background

Low-density parity-checking is an error correcting code used for robust communications, originally developed in 1960 by Robert G. Gallager.

Communications System Overview

Project Deliverables

GUI - a GUI that can take user input such as LDPC matrix size and produce all coded needs to create the LDPC system on an FPGA
Test Platform - a test platform that can test to make sure the LDPC system is working correctly.

Project Requirements

Engineering Specifications

Needs Assessment v1.0

Needs Assessment v1.1

Project Development

The final product is a test platform in which random messages are encoded, passed through a noisy channel model and finally decoded. This test platform evaluates the LDPC System and gathers statistics on its performance capabilities.

Data Flow Chart

Data Flow Chart

The Graphical User Interface is a Java application meant to be used by D3 Engineers to generate encoder and decoder models to produce a desired LDPC System for a particular FPGA.
GUI

GUI

MATLAB simulations were run to determine appropriate design parameters, such as numerical representation (i.e. fixed point), to ensure that the LDPC System meets customer requirements.

Concept selection was also performed at this phase of the project. It was an analysis of the trade-offs between different choices that could be made in the design.

Concept Selection v1.0

Concept Selection v1.1

We outlined potetential risks and steps we could take to mitigate them.

Risk Plan v1.0

Risk Plan v1.1

Risk Plan v1.2

Project Design

Our design phase included many revisions of block diagrams presented to the customer during our Design Reviews.

Design v1.0

Design v1.1

Preliminary Design v1.0

Preliminary Design v1.1

Preliminary Design v1.2

LDPC Design v1.0

LDPC Design v1.1

LDPC Design v1.2

LDPC Design v1.3

LDPC Design v1.4

Project Results

Bit Error Rate

The bit error rate required for the LDPC system was 10-4 at a SNR of 7 dB. Our system meets this requirement for all tested cases.
Bit Error Rate of System

Bit Error Rate of System

Decoder Bit Rate

The decoder bit rate required for the LDPC system was 105. The 1/2 rate decoders meet this requirement at 11 dB. The 1/4 rate decoder does not meet this requirement due to the lower code rate and because the decoder is not fully optimized for the binary case.
Decoder Bit Rate

Decoder Bit Rate

Encoder Bit Rate

The encoder bit rate required for the LDPC system was 105. All test cases passed this requirement.
Encoder Bit Rate

Encoder Bit Rate

Testing

The results were gathered in accordance with the test plans developed early in the project design phases.

Test Plan v1.0

Test Plan v1.1

Test Plan v1.2

Test Results v1.0

Test Results v1.1

Test Results v1.2

Future Work

Future Work v1.0

Future Work v1.1

Future Work v1.2

Future Work v1.3

Future Work v1.4

Administrative

Bill of Materials v1.0

Bill of Materials v1.1

Bill of Materials v1.2

Project Schedule