Table of Contents
Tuesday, April 24, 2007Meeting started 5:00pm in Prof. Slack's office. Jason, Adam, and Prof. Slack were in attendance.
Adam drew a dry-erase version of the board layout, and Prof. Slack brought up the idea of the daughter board "playground" and how to interface to it. He suggested one large header, which would then be split into constituent headers on the daughterboard. He asked how the USB to JTAG unit would accept two USB or one USB and one serial, but we need more info on the unit itself to accurately assess its capabilities.
Prof. Slack informed us that we would soon need a "bill of materials", and Adam voiced concern that Rob hadn't yet completed the power design. We also need a finished schematic by the last week, but that requires design of each part not included in the Capture library. Jason volunteered to design the iCoupler and WiPort parts for the schematic. Adam and Rob will split the other parts.
Adam obtained a ZIP file of developer source code from LANTronix, which he forwarded to Jason for analysis and development. Jason e-mailed Prof. Slack the 11-week schedule in PDF format.
Thursday, April 26, 2007Meeting started 4:00pm in SD atrium. Jason, Adam, Rob, and Prof. Slack were in attendance.
Prof. Slack mentioned that the design review went well, but no one seemed interested in the PCB layout software. Maybe host another design review (15-30 min) for that. Get Patru involved - he wasn't in the last one. Rob should bring examples different PCB layout software.
Adam debated the merits of use anything but Allegro if the EE department is set on using Allegro. Adam likes Altiem. Tactical vs. strategic - Short term is Allegro, long-term may be something else.
Rob asked about paying for parts that we can't get samples for - Prof. Slack recommended filling out a requisition form.
Adam is getting a new SuperPhone after May 1.
Jason needs to update Needs Assessments (programming interface section)
Adam uploaded a new board layout sketch on Edge.
We need a Bill of Materials for all electronic components.
Power issues debated - heat dissipation would be required for the original 12V design. Prof. Slack suggested having a separate "power board" that will have 5V regulation. Adam says that designs should provide 5V through a wall wart while prototyping, and it will be up the the design team to regulate their project's power down to 5V for the final design. Rob thinks that someone could still hook up a dangerous input supply to the board, but we can design so that protection circuitry will keep the board from blowing up. We will give design teams 5V out, but we won't let them use the 3.3V or 1.8V inputs of the DSP in order to keep those lines as clean as possible.
Need a user manual to spec out everything in the paragraph above.
Need a plan for the user manual and the Allegro document. Allegro document should not be anything from scratch.
LANTronix called. A fix is on the CD - Jason will run that at home.
Tuesday, May 1, 2007Meeting started at 4:00pm. Jason, Rob, and Adam are in attendance.
Two main reviews on the 11th - schematics, CAD tutorial plan, board tutorial plan and overall design (test plan, cost, etc.). Discuss bill of materials Thursday.
Detailed design review CAD tutorial Package is Allegro Assumptions
- Who is user? - Senior design student/mentor
- What is skillset? - 4th yr/5th year CE/EE/ME
- Write with mechie in mind
- User will have access to full manual
- EMA available for the student, not required by tutorial
Table of Contents
- Intro (purpose of tutorial, assumptions)
- Starting Allegro
- Defining new project
- Filling in title block
- Creating new library
- Creating new parts
- Decal (footprint)
- Adding existing (Capture) parts
- Assigning PSPICE model to a part
- Keeping design library clean
- Design library vs. Cadence library
- Creating new parts
- Directory structure (maybe)
- Creating a schematic in Capture
- Place symbol reference from libraries
- Adding ports
- Using buses
- Creating a layout from schematic
- Exporting design to PCB Layout
- Design rules (minimum spacing, etc)
- Define number of layers
- Two ways of creating board : one before placement (fixed board size), one after placement (minimal size)
- Placing parts
- Additional Board tricks
- Layout down parts en masse or individually
- Create dogbones
- Hide ratlines for manual routing
- Manual vs. autorouting
- Clean edges
- Back Annotation to schematic
- Defining power planes
- Silkscreen layers
- Exporting layout for fabrication
- Board fabrication
- screamingcircuits.com allows quotes from Gerber files
- Give a contact for CIMS and external company for population
- Definitions (abbreviations and such)
- High level overview of capabilities and layout
- Programming the microcontroller
- I/O pins
- Playground board layout
- Power board
- Program a sample program
- Hook up debug (PWM)
- Flash a light on playground board
- Accessing WiPort debug
Include CD with PDFs and sample programs
- Directory structure
- Code Composer
- Documentation above
- Drivers for USB
- Tutorial Support
- Demo programs
Adam does higher-level integration for schematic CAN tranceiver will be moved to playground board
Have a basic draft of tutorial PLANS by Friday
Symbol library *IMPORTANT* - done by Thursday
- WiPort interface pins
- Supporting hardware
- Voltage sense
- Current sense - done by Rob
- CAN tranceiver
- Memory module
- I/O and Power
- Design debounced switch - JASON
- Supporting hardware for WiPort
- Find out hardware required to interface with power sense and debug
Rob needs to design overvoltage protection with PTC and diode
Probe board needs to be designed as well
Rob is responsible for designing power bus
Integration on Friday
Thursday, May 3, 2007Meeting started at 4:00pm. Jason, Rob, and Adam, Dr. Slack are in attendance.
Discussed voltage regulators
Discussed Friday's lecture and our groups presentation requirements. meeting 9:00 CEDA lab friday 5/4/2007
Altium opened their new office in Mass, New account manager started monday.
discussed power and memory bus, having seperate grounds on the board, to reduce current loops
decoupling capacitors on IC'd, capacitor placement should be examined on eval board.
covered wifi port, converting its serial to USB and, how will we convert the serial to USB for programming. wifi may have a clock to sync serial comminication?
spoke with dr phillips about using a mux and a jumper to have optional memory space on the pcb.