Table of Contents
The Automated TFT Noise Characterization platform's design files are located at the following location:
Authorized users can access this directly with a SVN client at the following link:
What follows is a description of each top-level folder.
This folder contains the files used to create the CPLD design.
The doc/ folder includes datasheets and a block digagram of the CPLD design from a high level.
The sim/ folder contains all of the inputs to run a simulation of the CPLD design: A MATLAB script to create a test vector input file, a VHDL testbench that reads the file, and a Modelsim .do script to perform a simulation.
The src/ folder contains the source code of the CPLD design.
The syn/ folder contains the required inputs to perform logic synthesis of the CPLD firmware. Note that ISE 11.1 was used to build the CPLD for this project. (The UCF should be downwards compatible with previous versions of ISE) This folder also contains the CPLD programming file atncp_cpld.jed.
Contains overall project documents produced during the course of MSD.
This folder contains the CAD documents used to design the RF/EMI shielding device used by the project:
seniordesignv3.prt.28: This file is a ProEngineer Student Edition part file. It contains a three dimensional representation of thetheoretical design of the part of Valhalla that holds the probe card in place, slides into the M150 measurement platform card holder, and provides the probe card access to the wafer.
seniordesignlowerinsertv2.prt.12:This file is a ProEngineer Student Edition part file. This file visually describes the insert which completes the continuous ground plane found in seniordesignv3.prt.28.
seniordesignupperv2.prt.27: This file is a ProEngineer Student Edition part file. It is a three dimensional CAD drawing of the portion of Valhalla that inserts into seniordesignv3.prt.28 on top of the probe card, holds the probe card in seniordesignv3.prt.28, provides a viewing window of the probe tips, and has the docking point for the box that contains the electronic components of the system.
seniordesignchipboxv3.prt.14: This file is a ProEngineer Student Edition part file. This three dimensional CAD drawing visually describes the box that contains the electronic components of the system and has a system by which to attach to seniordesignupperv2.prt.27.
seniordesignlidv1.prt.4: This file is a ProEngineer Student Edition part file. It contains a three dimensional representation of the lid for seniordesignchipboxv3.prt.14.
seniordesign.asm,7: This file is a ProEngineer Student Edition assembly file. It is a compilation of the basic part files seniordesignv3.prt.28, seniordesignlowerinsertv2.prt.12, seniordesignupperv2.prt.27, seniordesignchipboxv3.prt.14, and seniordesignlidv1.prt.4. This assembly visually depicts how the system theoretically fits together.
This folder contains the source code (in the form of LabVIEW Virtual Instruments) used by the project. It is divided into three folders.
Doc contains the pin assignments used for the DAQmx virtual channels that are connected to the CPLD.
The CPLD Control folder contains the VIs used to communicate with the CPLD. CPLDWrite.vi is responsible for the low-level bit banging used by each *Register.vi to set up the Viking board for the appropriate operation mode. CPLDDebug.vi provides a nice user interface to send values to/from the CPLD and examples on how to configure the board.
The Instrument Control folder contains VIs to communicate with the DSA. DSAMeasurement.vi contains a LabVIEW Instrument I/O assistant script to control the DSA, and the ATNCPHP3562A.vi is a modified version of an open-source DSA driver which reads data from the DSA. Note that a DSA GPIB address of 20 is hard-coded into both of these VIs.
The main VI which automates a measurment process is Viking.vi.
Viking Hardware Design
The Viking Hardware folder contains all of the relevant schematics and layout files for the Viking project. All files are formatted for use in ExpressPCB and ExpressSCH, both of which are freely available. VikingFunctional.sch is a very readable functional schematic of the project, which allows operation of the circuit to be understood more easily than a full schematic. Likewise, VikingFunctional - Analog.sch is the same schematic with all of the digital components removed to allow for a more readable analog schematic.
Viking.sch is the complete and full schematic from which the PCB layout was created.
Viking.pcb is the first revision of the board and is currently being tested and demonstrated.
Viking_2.pcb is the second revision of the board. Changes from the first revision are based off problems encountered with the first revision and documented in the Senior Design Rework Progress.xls file.