P10662: D3 Engineering Camera Platform

Software Design

Table of Contents

Software Design

The software runs on two separate processing devices, the DSP provided by the customer, and the Complex Programmable Logic Device (CPLD). These two devices will work in tandem to provide a faster, streamlined level of functionality.

The design can be broken down into 3 main groups, the Image capture and imager configuration portion, the CPLD VHDL design, and the GPS/IMU and other extra functionality

Image Capture/Imager setup

The main function of the system was capture images using the in-system imagers. These imagers need to be configured before image capture begins, this includes setting up items such as the exposure time, the area of the sensor to capture, etc. The basis for this code was some sample code for another model of sensor provided by the customer. This was taken and modified for use by the team for the specific imagers in the system. Some extra functions were added to interface with the included hardware that was added to accurately allow communicaton on the CPLD board. Another part of this design was to compress the images into a JPEG format and save them to the SD card. This functionality was again modified from sample code given by the customer. With all of the modifications that took place during the design, the resulting software doesnt resemble in anyway the initial given code from the customer.


The CPLD was to provide the actual switching functionality as well as other lower level function for the system. At a basic level, the software design for the CPLD was to take inputs from the DSP software and use them to configure the streaming image data from the imagers. It provided a switching ability for the DSP to choose on demand, which imager to recieve the data from, as well as to program the imagers.


This part of the software was to run on the DSP and interface with the GPS & IMU devices in a hardware interrupt fashion. This will allow more processing power to be used for other functions instead of waiting on I/O. The basic functionality was to use a UART through the use of Rx/Tx lines for simplicilty and reduced computation the DSP.
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