P13571: Video Analytics
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Build, Test, Document

Table of Contents

The responsibilities involved in the construction of the design were naturally divided into sections related to the engineering fields of the team members.

The enclosure design, build, and testing were managed by the mechanical engineers. The housing was built by ProtoLabs, a prototype machining company, using a CNC machine uploaded with the team's design file. Thermal and modal simulations were created in Pro-E (Creo Parametrics) and Solidworks, and then the actual device was tested with thermocouples.

The electronics design was created by the electrical engineers. Gerber files and fabrication drawings were created and sent to a manufacturer for construction. Upon reception of the assembled circuit boards, short checks were conducted and proper voltages were measured at the output of the different regulators. The functionality of the JTAG connection, flash memory, and I2C communication with the image sensor were additional parts of the test plan.

Finally, the software design was implemented by the computer engineers. A two stage design was created in the FPGA using Verilog HDL. Each block of the design was tested individually using the on-chip logic analyzer, SignalTap II. This allowed the engineers to rapidly test blocks of the design using the actual hardware.

Build, Test, and Integrate

Build

FPGA Assembly Drawing

public/Photo Gallery/Boards/FPGA_Assemblydrawing.JPG

Top Copper Layer Bottom Copper Layer

public/Photo Gallery/Boards/topcopperFPGA.JPG

public/Photo Gallery/Boards/bottomcopperFPGA.JPG

Software Data Flow

Software Data Flow

Tests

Integrate

Test Plans & Test Results

Test Plans

Test Results

Sealing Testing

The first iteration of O-ring groove geometries allowed for a compression range of 20-40% (depending on machining tolerance). Although this compression allows for maximum sealing, it did not allow for easy assembly. Thus, the groove geometry was changed in the model, allowing for 15% compression in the most recent CAD model. Additionally, the ordered parts were slightly different dimensionally than the CAD provided on their website, which affected the seal pressure. Concluding that the seals were either under or over compressed which left room for significant improvement after the first iteration. The CAD has been modified accordingly.

Thermal Testing

Convective Heat Transfer Coefficient

Convective Heat Transfer Coefficient

This test is to determine the accuracy of the Heat Dissipation Simulated results to the experimental results. In this test, the system is in the worst case scenario, which is natural convection.
  • Using Matlab, the Convective Heat Transfer Coefficient that each of the surfaces experience if the system is mounted up-right and flat (fins are parallel with the heat rise) are estimated and tabulated in the table to the right.
  • The Convective Heat Transfer Coefficient values along with the Conductivity of each material involved in the dissipation of heat, as listed to the right, are used in the Simulations.

The test is conducted with the system suspended (as shown in the Testing Set-up) so as to limit heat conduction through contact with other bodies. This is done so that the results can be compared to the simulated predictions, which assume that there is no contact with other bodies.

In order to simulate the heat generated by the FPGA (on the FPGA board) or the Inductor (on the Coax Board), six 16ohm resistors were soldered in series and embedded into an epoxy to provide an even heat generation through the contact surface and approximately 1Watt of heat. Two thermo-couples were used in the test; one to measure the temperature rise on the Heat Generator and the other to monitor ambient temperature.

Material Conductivity

Material Conductivity

Testing Set-up

Testing Set-up

FPGA Surface Temperature

FPGA Surface Temperature

Two tests were conducted:
  • The fist involved the Heat Generator simulating the FPGA with 1Watt of heat output.
  • The second involved the Heat Generator simulating the Inductor with 1Watt of heat output.


The graphs show the best fit line through the data obtained, as the raw data is extensive and is found in the attached document below. The equation used for the best fit line is the Transient Heat Transfer equation, in which b is the time constant of the system. This time constant is particular to this system and should not be used in any other set-up.

Using the Transient Heat Transfer equation, the steady state temperatures and temperature differentials were estimated. Next, a lump body assumption was used to calculate a Lump Body Resistance, as show by the equation, which was used to compare to the simulated results. Since the surface area through which the heat transfer is acting through is not a simply define but is constant, it can be combined with the thermo-resistance of the system, R, to obtain the Lump Body Resistance. This is calculated so that for any amount of heat generation, the temperature differential can be calculated along with the steady state temperature, if the ambient temperature is known.

Heat Generator (6 X 16ohm Resistors)

Heat Generator (6 X 16ohm Resistors)

Inductor Surface Temperature

Inductor Surface Temperature

Transient Heat Transfer

Transient Heat Transfer

Results & Comparison

Results & Comparison

The results show that, in comparison to the simulations, there is a small amount of error: 7.10% and 6.10% for the FPGA and Inductor Lump Resistances, respectively. This can be accounted for by the less than ideal set-up but for the purposes of this experiment, this amount of error is negligible and it can be assumed that the simulations are accurate to within 10%.

It can also be noted that anodizing the aluminum body has little to no effect on the steady state temperature but it has significant effects on the transient curve. The set-up has the Inductor side of the body anodized while the FPGA side has yet to be anodized. Given the same heat output, in the transient results, the FPGA takes about 30 minutes to reach steady state while the Inductor only take about 5 minutes to reach steady state, which means that the anodized aluminum is restricting the heat flow from the Inductor to the outside and causing the Inductor to reach steady state much faster than the FPGA.
Lump Body Resistance

Lump Body Resistance

Software Testing

Image Header Results

Image Header Results

Packet Header Results

Packet Header Results

Assembly Instructions

Assembly Instructions
Exploded View

Exploded View

  1. Place adhesive thermal pads on Housing, Cold Finger, and PCBs.
  2. Add Gaskets.
  3. Assemble PCB stack with Sensor Mount.
  4. Adjust M12 lens and shim Sensor PCB with 0.0254mm (0.001”) shims into focus to counteract sensor soldering tolerance.
  5. Slide Assembly into rear housing and fasten the coax HD-BNC connector.
  6. Slide Housing Front (M12 / M3-F or C-Mount Housing Front).
  7. Screw 4 socket-head screws into housing.
  8. Add Lens Cover or C-Mount Lens.

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