Build, Test, Document
Table of Contents
The responsibilities involved in the construction of the design were naturally divided into sections related to the engineering fields of the team members.
The enclosure design, build, and testing were managed by the mechanical engineers. The housing was built by ProtoLabs, a prototype machining company, using a CNC machine uploaded with the team's design file. Thermal and modal simulations were created in Pro-E (Creo Parametrics) and Solidworks, and then the actual device was tested with thermocouples.
The electronics design was created by the electrical engineers. Gerber files and fabrication drawings were created and sent to a manufacturer for construction. Upon reception of the assembled circuit boards, short checks were conducted and proper voltages were measured at the output of the different regulators. The functionality of the JTAG connection, flash memory, and I2C communication with the image sensor were additional parts of the test plan.
Finally, the software design was implemented by the computer engineers. A two stage design was created in the FPGA using Verilog HDL. Each block of the design was tested individually using the on-chip logic analyzer, SignalTap II. This allowed the engineers to rapidly test blocks of the design using the actual hardware.
Build, Test, and Integrate
- Enclosure Design
- The 6061-T6 Aluminum enclosure was designed to meet the requirements and customer specifications. The CAD drawing are under the "Planning and Execution" page. The housing was machined by FIRSTCUT due to their fast turn around times. The housing was then Anodized by Coating Technologies Inc in Rochester.
- To ensure the enclosure met the IP64 standard (Splash Resistance), Buna-N o-rings were chosen as the sealing method. The o-rings have a temperature resistance above 125°C to withstand high temperatures and are designed to have sealing pressure of 3.35MPa at 15% compression (a water depth of 350m, ensuring water water tightness).
- Heat Analysis
- The electrical components within the enclosure will generate 0.5 - 1.5 Watts of heat. The cooling load must be dissipated by the enclosure through natural convection and conduction. Using FEA software, the heat flow was analyzed to determine the heat dissipating capabilities of the enclosure.
- Modal Analysis
- This analysis was performed to determine the integrity of the enclosure design. FEA software was used to determine the natural frequency of the assembly and then compared to frequencies the camera system will experience in an automotive application.
- Enclosure Design
- Electrical/Hardware Design
Schematics and PCB Layout
- The schematic designs were created using Orcad Capture CIS. The designs were then netlisted into Orcad PCB Editor, which means all the components and nets were identified by the software to avoid differences between the schematic and component placement/connections.
- The FPGA board is the most complex design of the board stack. This board has 8 layers: 4 signal, 2 power, and 2 ground. The board has 100-ohm controlled impedance layers for the differential pairs from the imager, the output of the transceiver, and the 156.25 MHz LVDS oscillator.
- The Power Board and Coax Board are 4-layer boards: 2 signal layers, a power layer, and ground layer. The Coax Board was also controlled impedance because it had a long differential pair transmission line, namely the high-speed downlink.
- The 14MP Imager Board is a 6-layer board: 2 ground layers, 2 power layers, and 2 signal layers. This board required high-density fabrication techniques, because the image sensor had very fine-pitch BGA footprint. The small drill sizes that were necessary required the board to be only .031" thick.
- Schematics and PCB Layout
|FPGA Assembly Drawing|
|Top Copper Layer||Bottom Copper Layer|
- Software Design
- The software data flow was primarily broken up into two stages, a capture stage, and a transmission stage. This was done due to different parts of the software being controlled by different logic in different domains.
- Each domain is handled by a controller that orchestrates the timing and data flow appropriately.
- In this stage, the pixel data is read in, in parallel and put into a FIFO
- At appropriate points in the reading in of data, an image header and line marker are added as meta data required by the Coax standard.
- In this stage, information is read from the FIFO and packetized with a CRC calculated over the information and sent with the packets.
- Upon being properly packetized, the data is sent through a transmitter to be sent across the transceiver.
- Mechanical Tests
- Drop Testing
- Drop tests should be performed to validate the structural integrity of the enclosure but do to limited quantity, the team has refrained from performing this test.
- Heat Dissipation Testing
- This test is designed to validate the enclosures capability to dissipated the anticipated heat generated by the electrical components during general operations.
- Water Spray Test
- This test is designed to test the integrity of the seals under one meter of water pressure. This test is only applicable to the M12 and M3-F assemblies; the C-Mount assembly is exempt from this test, as the lens is mounted externally.
- Dust Tight Test
- This test is designed to comply with the IP64 standard, which requires the inner components to be free of dust. This task was reached by passing the IP64 water resistance standards.
- Drop Testing
- Electrical Testing Documentation
- Software Tests
- Line Generator Test
- This test was designed to ensure the correct meta data was put out at appropriate times when new line and new image values asserted.
- Packetizer Test
- This test was designed to ensure the correct meta data was put out at appropriate times when packet header and packet trailer values were asserted by the controller.
- Line Generator Test
Test Plans & Test Results
- Mechanical Test Plans
- Circuit Board Tests
- Software Test Plan
Sealing TestingThe first iteration of O-ring groove geometries allowed for a compression range of 20-40% (depending on machining tolerance). Although this compression allows for maximum sealing, it did not allow for easy assembly. Thus, the groove geometry was changed in the model, allowing for 15% compression in the most recent CAD model. Additionally, the ordered parts were slightly different dimensionally than the CAD provided on their website, which affected the seal pressure. Concluding that the seals were either under or over compressed which left room for significant improvement after the first iteration. The CAD has been modified accordingly.
This test is to determine the accuracy of the
Simulated results to the experimental results. In
this test, the system is in the worst case scenario,
which is natural convection.
The test is conducted with the system suspended (as
shown in the Testing Set-up) so as to limit heat
conduction through contact with other bodies. This
is done so that the results can be compared to the
simulated predictions, which assume that there is
no contact with other bodies.
Two tests were conducted:
The results show that, in comparison to the
simulations, there is a small amount of error: 7.10%
and 6.10% for the FPGA and Inductor Lump Resistances,
respectively. This can be accounted for by the less
than ideal set-up but for the purposes of this
experiment, this amount of error is negligible and it
can be assumed that the simulations are accurate to
It can also be noted that anodizing the aluminum body has little to no effect on the steady state temperature but it has significant effects on the transient curve. The set-up has the Inductor side of the body anodized while the FPGA side has yet to be anodized. Given the same heat output, in the transient results, the FPGA takes about 30 minutes to reach steady state while the Inductor only take about 5 minutes to reach steady state, which means that the anodized aluminum is restricting the heat flow from the Inductor to the outside and causing the Inductor to reach steady state much faster than the FPGA.
- Line Generator test
- For this test, a test module was created that would at certain points assert a send image header or send line marker value. Upon assertion the line generator would then be in "sendingxxx" mode and output those values on its output bus. The results can be seen below for an image header being sent:
- Packetizer test
- For this test, a test module was created that would at certain times assert a send packet header or send packet trailer value. Upon said value assertion the packetizer would then be in "sendingxxx" mode and output the appropriate values on its bus. The results can be seen for a packet header: