Build, Test, Document
Table of Contents
Website should document your journey through MSD, so include work-in-progress as well as latest results. Use pdf's for display whenever possible so that information is easily viewable without the need to download files and open applications. (Your EDGE file repository should still contain original files).
Sample categories are listed below, but feel free to change or add nodes to better correspond to your project and your Guide’s expectations.
Status Updates and Action Items
Alonso - Responsible for carrying out the heat analysis of the enclosure and helping Matt with detailed drawings of individual components.
Matt - Responsible for detailed drawings of components along with Alonso.
FPGA Board Subsystem
As of now the work on the FPGA schematic has been put on hold so the software development can begin.
CXP HSMC Subsystem
Steve Brown is currently working on the CXP HSMC PCB layout working from where Lennard left off.
Jordan - Responsible for Qsys to integrate the SoC and the FPGA. Many of the busses and registers will need to be mapped from the FPGA to the SoC so the SoC can dynamically adjust the characteristics of the FPGA. There are references to overall designs of Qsys systems, but we will need to develop a custom mapping of the Qsys signals.
Lennard - Responsible for overall Verilog architecture.
Kyle - Responsible for ARM core communication with FPGA. This part will consist of booting up the hard processor, establishing connection with FPGA, and sending commands from the ARM core to FPGA. The ARM core will be responsible for controlling the FPGA functions ”on the fly” while processes on the FPGA are running.
As of now most of the work has been a group effort to get the basic parts of the FPGA setup. This includes getting QSYS files setup, system files setup, and to get everything else setup to match the D3 setup.
Action ItemsAction Items for week 11/3/2014 - 11/10/2014
Mechanical Action Items:
Mechanical Design Review 11/6/2014
Hardware Action Items:
Status Update from D3 on CXP HSMC PCB layout
Software Action Items:
Complete System File
Complete QSYS setup
Work with Steve to get an understanding of the next steps
Other Action Items:
Update Project Plan
Continue working on Final Presentation
Continue working on Final Technical Paper
Update EDGE with new material
Build, Test, and Integrate
Updated CAD Models
Test Plans & Test Results
Embedded Design Suite "Hello World" Test Plan and Results
Results from EDS Hello World Test Plan Execution. Bottom right shows the Application Console displaying "Hello World!"