P16221: FSAE shock dyno
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Systems Design

Table of Contents

Team Vision for System-Level Design Phase

Summarize:

Functional Decomposition

Functional Decomposition

Functional Decomposition

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Benchmarking

Download Benchmarking Document

Concept Development

Morphological Chart and Concept Selection

Morphological Table

Morphological Table

Download Morphological Table

Morphological Table With Highlighted Concepts

Morphological Table With Highlighted Concepts

Concept Selection

Concept Screening

Concept Screening

Concept Screening Matrix

Systems Architecture

System Design Flowchart

System Design Flowchart

System Level Design Flowchart

Feasibility: Prototyping, Analysis, Simulation

Memory Required to Store an Hour of Track Data

Assumptions:

Calculations:

Total number of samples = 3,600 seconds * (500 samples/sec) + 1 = 1,800,001 samples. The +1 is because we are starting at t=0.

Total number of bytes = 1,800,001 samples * (8 bytes/sample) = 14,400,008 bytes = 14,062.5 kB = 13.74 MB.

Comments/Considerations:

RS-232 Serial Speed Analysis

Assumptions:

Calculations:

64 bits of data in 0.002s = 32,000 bits per second

Comments/Considerations:

Load Cell Analysis

Assumptions:

Calculations:

Comments/Considerations:

Microprocessor Read Speed Test

Assumptions

Sketch

Sketch

Sample Run

Program Output

Data Analysis

Comments

At a maximum scan time of 432 us, we should have plenty of time left to move the actuator, send the data to the host PC and receive more track data to achieve the 125 Hz control speed requirement. Careful consideration should be taken to not perform too much as the 5 variables in the sketch took up 16% of the available stack space on the microprocessor.

Risk Assessment

Risk Table

Risk Table

Risk Management Document

Design Review Materials

Plans for next phase


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