P17342: IC Test Bed for Electronics Lab
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Project Summary Project Information

For our initial project description, click on the following link for the Project Readiness Package.

Electronics labs require students to design, build, and debug circuits in order to characterize behaviors and gain an understanding of underlying principles. Students utilize various integrated circuit (IC) chips to facilitate their testing. Often times chips may be presumed non-functional due to user error. Furthermore chips may be partially/fully broken by issues like over voltages/currents, improper pin assignments, etc...

To rectify this, our team is aiming to create a generalized IC testing rig, capable of characterizing chips and their possible malfunctions. It must be capable of testing the basic range of chips used in Electronics labs, with the ability to handle future additions. With a target price range of 50-75$, the challenges will lie firmly in the acquisition and design of a simple, yet capable implementation along with it's veracity and repeatability.

Project Name
IC Tester
Project Number
P17342
Start Term
2165
End Term
2171
Faculty Guide
Professor Slack
Primary Customer
Professor Fuller
Sponsor (financial support)
RIT
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Team Members

Left to right: Matthew, Benjamin, Nicolas, Brian, Hamza, David, Zachary

Left to right: Matthew, Benjamin, Nicolas, Brian, Hamza, David, Zachary

Member Role Contact
David Froehlich Lead Engineer df3947@g.rit.edu
Nicolas Guerrero Facilitator ndg3986@rit.edu
Matthew Hohman Purchaser mth7650@rit.edu
Benjamin Lane Communications btl6309@rit.edu
Hamza Masood Engineer hxm4180@g.rit.edu
Brian Mesolella Project Manager btm1307@rit.edu
Zachary Kruse Software Engineer zak1028@rit.edu

Table of Contents

MSD I & II MSD I MSD II

Planning & Execution

Project Photos and Videos

Imagine RIT

Problem Definition

Systems Design

Preliminary Detailed Design

Detailed Design

Build & Test Prep

Subsystem Build & Test

Integrated System Build & Test

Integrated System Build & Test with Customer Demo

Customer Handoff & Final Project Documentation

Acknowledgements