Team Vision for Detailed Design PhaseTeam 18262 set out to create the circuit card layout, create all test plans for hardware validation, and firmware functionality documentation. This would allow the team of order the boards over the break between MSD 1 and MSD 2. Along with ordering all the parts before break, the team would would be able to immediately start populating the board, to begin hardware validation.
During this phase the team was able to get the board layout of both the master and slave boards created. Due to a sponsorship from Advanced Circuits, the team is able to send out our project to be fabricated over the break. Due to the BOM created in the PDDR, all parts are able to be ordered. No parts are expected to be long lead, so it is expected that at the beginning of MSD 2 the team will be able to start populating the boards. Test plans have been created to build a comprehensive path of action to validating the boards functionality as soon as the boards are populated. Overall the team was able to meet out initial plans for this phase.
MSD 1 Goals
Overall, the team planned to have a complete board layout and design for the end of MSD 1. This would allow the boards to be ordered by a PCB manufacturer to be completed by the time MSD 2 starts. In tandem with this, all necessary parts would be ordered, so board population and validation could begin at the start of MSD 2. These tasks were accomplished, and board and part orders are to be sent out after the Detailed Design Review.
The team was also able to accomplish the following which directly led to the success of the stage.
- Iterative Design throughout the process from concept selection to final design.
- Significant troubleshooting, the need for development boards were quickly identified and ordered allowing for weeks of testing before final design was due.
- Designs reviewed by subject matter experts, from RIT professors to industry professionals
MSD 2 Goals
The team is in a good position to start MSD 2, with boards and parts ready to be put into use at the beginning of the stage. Significant time has been allocated for validation and test, as well as time for a respin of the boards in case a showstopping issue is found.
Prototyping, Engineering Analysis, Simulation
The majority of prototyping and simulation has been created and documented in the Preliminary Design Review. For the Detailed Design Review the Thermistor Prototyping was completed as separate from the board. All other simulations can be found in the Preliminary Design Review section.
At the end of the PDDR, the thermistors setup had been tested using LTSpice. To give a real-world test, the thermistor was tested using a thermometer, container of water heated to 100C, and a multimeter. This allowed for the thermistor to be tested from the range of 100c to 0C, and provide data on the accuracy and performance of the thermistor.
Trial 1 of the test used the addition of ice to cool the test, however this was found to create hot and cold spots in the tested that created inaccuracies. This was changed to having the water cool passively over the course of the test. The results from trial 2 show a more accurate result. The raw data acquistion has a section on the plus or minus resistance expected to ensure a 2C accuracy. This was found by gathering the range of resistance values between each 10C rating given on the datasheet, and dividing it by 5 to get the 2C resistance value. All values found in trial 2 met this requirement. Both engineering requirements are proven in this testing.
Wiring and Connectors
The following image details the layout of the wiring of the boards, with wire amounts and wire gauges. The connectors are the connector splices used instead of wire splicing. There are 13 cell wires for the top and bottom of the stack, and all the ones in between. Each cell wire connectors to the positive and negative terminals of the cells.
Drawings, Schematics, Flow Charts, Simulations
Master Board Images
Slave Board Images
Subfunction Flowcharts and Requirement Trace ability
All theoretical simulation work was completed in the Preliminary Detailed Design Review. Test plans were created for simulation in MSD when the board has been populated.
Links to Test Plans
A link to the Firmware test plans can be found here
A link to the Master test plans can be found here
A link to the Slave test plans can be found here
Bill of Material (BOM)
The BOM can be found here
Advanced Circuits has awarded the team a $500 credit towards board production. This is part of their Engineering Student Program. This generous donation will allow the team to stay within budget for the project.
Testing Standards UsedAs part of the Advanced Circuits Sponsorship, the boards were designed based off the standards provided by Advanced Circuits to ensure functionality as well as reduce cost. This is accomplished by following the standards allowing the circuit cards to be produced easier.
Pikes Peak International Hill Climb has a number of electrical standards which our team will need to consider when developing our REV2 motorcycle. Of those, two specific standards are extremely relevant to our project. Relevant Competition Standards “All exposed conductors operating at greater than 36V must be properly insulated and marked with ‘High Voltage’ signs”. “A separate fuse (not a circuit breaker) will be placed in series with the main battery and the rating will not exceed 200% of the maximum expected current draw. All low voltage taps from the main battery will be separately fused. All fuses must be placed first in series with the battery starting at the positive connection”. The first can be mitigated with proper enclosure design, in addition to careful labeling in the harness and on the PCB. The second has been considered in the selection of individual fuses on all of the battery management system measurement points. These regulations are important for ensuring the safety of all competitors in the electric vehicle class. A full pdf of the 2017 competition rules can be found here: PDDR/PPIHC_Rulebook.pdf
Design and Flowcharts
This figure shows the decreasing risk importance, which is the sum of the importance column in the risk table. This allows the team to track how the risks change over the course of the project.
- Resource, PCB's Manufactured Incorrectly
- Technical, Issues with board wiring in the battery box
The following items were downgraded in severity, which is from the team coming up with ways to solve the issue. Other risks are no longer a problem, such as late delivery of the development boards as all have arrived.
- Safety, sparking caused by voltage spikes, this is minimized because all voltage planes are low enought voltage to not have any issue from spiking. Pack Voltage is isolated from all other voltages and ground plans.
- Environmental, electro-static discharge failures, this is minimized as all parts are low ESD, and the team will be working in the Surface Mounting Lab, with ESD procedures taken into account.
- Technical, mounting issues on motorcycle, this is minimized as all mounting holes are approved by the mechanical teams at EVT, and use standard hole sizes
- Resource, Over Budget, this is minimized by sponsorship's from advanced circuits
- Resource, Late Delivery of Parts, this is minimized as all parts are not long lead and in stock.
- Technical, Project does not meet requirements, this is minimized as all customer and engineering requirements have trace-ability to a sub-function of the project.
- Social, Team disagreements on the project, the team is in agreement on the path to take and what the project consists of.
- Resource, Timely Delivery of development board, all boards have been delivered
- Technical, Connectors do not satisfy requirements, this is minimized as chosen connectors have all pins needed, and meet the size requirements.
- Resource, PCB's are manufactured incorrectly, this is minimized by going with an approved and professional board fabrication company.
The following item has increased its risk, and is currently being worked on
- Technical, State of Charge chip testing does not get completed in time, this is being debugged, and the team has contacted technical subject matter experts at Texas Instruments to help resolve the issues being found.
Design Review Materials
A link to the design review can be found here
A link to the pre-read can be found here
Plans for next phase
Individual Plans Three week plans created after the last design review are here, and are compared to what was completed. The three week plan for the next section are also included.