P18262: Battery Health Management System
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Detailed Design

Table of Contents

Team Vision for Detailed Design Phase

Team 18262 set out to create the circuit card layout, create all test plans for hardware validation, and firmware functionality documentation. This would allow the team of order the boards over the break between MSD 1 and MSD 2. Along with ordering all the parts before break, the team would would be able to immediately start populating the board, to begin hardware validation.

During this phase the team was able to get the board layout of both the master and slave boards created. Due to a sponsorship from Advanced Circuits, the team is able to send out our project to be fabricated over the break. Due to the BOM created in the PDDR, all parts are able to be ordered. No parts are expected to be long lead, so it is expected that at the beginning of MSD 2 the team will be able to start populating the boards. Test plans have been created to build a comprehensive path of action to validating the boards functionality as soon as the boards are populated. Overall the team was able to meet out initial plans for this phase.

Progress Report

MSD 1 Goals

Overall, the team planned to have a complete board layout and design for the end of MSD 1. This would allow the boards to be ordered by a PCB manufacturer to be completed by the time MSD 2 starts. In tandem with this, all necessary parts would be ordered, so board population and validation could begin at the start of MSD 2. These tasks were accomplished, and board and part orders are to be sent out after the Detailed Design Review.

The team was also able to accomplish the following which directly led to the success of the stage.

MSD 2 Goals

The team is in a good position to start MSD 2, with boards and parts ready to be put into use at the beginning of the stage. Significant time has been allocated for validation and test, as well as time for a respin of the boards in case a showstopping issue is found.

Prototyping, Engineering Analysis, Simulation

The majority of prototyping and simulation has been created and documented in the Preliminary Design Review. For the Detailed Design Review the Thermistor Prototyping was completed as separate from the board. All other simulations can be found in the Preliminary Design Review section.

Thermistior Prototyping

At the end of the PDDR, the thermistors setup had been tested using LTSpice. To give a real-world test, the thermistor was tested using a thermometer, container of water heated to 100C, and a multimeter. This allowed for the thermistor to be tested from the range of 100c to 0C, and provide data on the accuracy and performance of the thermistor.

Thermistor Requirements

Thermistor Requirements

Thermistor Results

Thermistor Results

Thermistor Graph

Thermistor Graph

Trial 1 of the test used the addition of ice to cool the test, however this was found to create hot and cold spots in the tested that created inaccuracies. This was changed to having the water cool passively over the course of the test. The results from trial 2 show a more accurate result. The raw data acquistion has a section on the plus or minus resistance expected to ensure a 2C accuracy. This was found by gathering the range of resistance values between each 10C rating given on the datasheet, and dividing it by 5 to get the 2C resistance value. All values found in trial 2 met this requirement. Both engineering requirements are proven in this testing.

Wiring and Connectors

Wiring Layout

Wiring Layout

The following image details the layout of the wiring of the boards, with wire amounts and wire gauges. The connectors are the connector splices used instead of wire splicing. There are 13 cell wires for the top and bottom of the stack, and all the ones in between. Each cell wire connectors to the positive and negative terminals of the cells.

Drawings, Schematics, Flow Charts, Simulations

Master Board Images

Master Figure 1:Isolated Communications Layout

Master Figure 1:Isolated Communications Layout

Master Figure 2: MCU Layout

Master Figure 2: MCU Layout

Master Figure 3: Master Board, Bottom Layout

Master Figure 3: Master Board, Bottom Layout

Master Figure 4: Master Board, Top Layout

Master Figure 4: Master Board, Top Layout

Master Figure 5: Master Board Top, 3D View

Master Figure 5: Master Board Top, 3D View

Master Figure 6: Master Board Bottom, 3D View

Master Figure 6: Master Board Bottom, 3D View

Master Figure 7: Master Board Dimensions

Master Figure 7: Master Board Dimensions

Master Figure 8: Master Board, 3D View

Master Figure 8: Master Board, 3D View

Slave Board Images

Slave Figure 1: Discharge Array

Slave Figure 1: Discharge Array

Slave Figure 2: LT3990 Layout

Slave Figure 2: LT3990 Layout

Slave Figure 3: LTC6811 Layout

Slave Figure 3: LTC6811 Layout

Slave Figure 4: Temperature Sensor Layout

Slave Figure 4: Temperature Sensor Layout

Slave Figure 5: 3D Layout of Slave, Back View

Slave Figure 5: 3D Layout of Slave, Back View

Slave Figure 6: 3D Layout of the Slave, Front View

Slave Figure 6: 3D Layout of the Slave, Front View

Slave Figure 7: DRC Check Pass

Slave Figure 7: DRC Check Pass

Slave Figure 8: Dimensions of the Slave Board

Slave Figure 8: Dimensions of the Slave Board

Slave Figure 9: 3D Image of the Slave Board

Slave Figure 9: 3D Image of the Slave Board

Requirements Flowcharts

Customer and Engineering Requirements

Customer and Engineering Requirements

Subfunction Flowcharts and Requirement Trace ability

BMS Chip Customer and Engineering Requirements

BMS Chip Customer and Engineering Requirements

Hall Effect Customer and Engineering Requirements

Hall Effect Customer and Engineering Requirements

MCU Customer and Engineering Requirements

MCU Customer and Engineering Requirements

Passive Balancing Customer and Engineering Requirements

Passive Balancing Customer and Engineering Requirements

State of Charge Customer and Engineering Requirements

State of Charge Customer and Engineering Requirements

EVT Implementation Customer and Engineering Requirements

EVT Implementation Customer and Engineering Requirements

Simulation

All theoretical simulation work was completed in the Preliminary Detailed Design Review. Test plans were created for simulation in MSD when the board has been populated.

Test Plans

Test Plan Setup

Test Plan Setup

A link to the Firmware test plans can be found here

A link to the Master test plans can be found here

A link to the Slave test plans can be found here

Bill of Material (BOM)

The BOM can be found here

Budget

Advanced Circuits has awarded the team a $500 credit towards board production. This is part of their Engineering Student Program. This generous donation will allow the team to stay within budget for the project.

Budget as of 12-5-17

Budget as of 12-5-17

Testing Standards Used

As part of the Advanced Circuits Sponsorship, the boards were designed based off the standards provided by Advanced Circuits to ensure functionality as well as reduce cost. This is accomplished by following the standards allowing the circuit cards to be produced easier.
 Advanced Circuits Requirements for boards

Advanced Circuits Requirements for boards

public/PDDR/ppihc.PNG

public/PDDR/ppihc.PNG

Pikes Peak International Hill Climb has a number of electrical standards which our team will need to consider when developing our REV2 motorcycle. Of those, two specific standards are extremely relevant to our project. Relevant Competition Standards “All exposed conductors operating at greater than 36V must be properly insulated and marked with ‘High Voltage’ signs”. “A separate fuse (not a circuit breaker) will be placed in series with the main battery and the rating will not exceed 200% of the maximum expected current draw. All low voltage taps from the main battery will be separately fused. All fuses must be placed first in series with the battery starting at the positive connection”. The first can be mitigated with proper enclosure design, in addition to careful labeling in the harness and on the PCB. The second has been considered in the selection of individual fuses on all of the battery management system measurement points. These regulations are important for ensuring the safety of all competitors in the electric vehicle class. A full pdf of the 2017 competition rules can be found here: PDDR/PPIHC_Rulebook.pdf

Design and Flowcharts

Functional Decomposition

Functional Decomposition

Risk Assessment

Risk Graph

Risk Graph

This figure shows the decreasing risk importance, which is the sum of the importance column in the risk table. This allows the team to track how the risks change over the course of the project.

Risk Table

Risk Table

The following items were added to the risk assessment

The following items were downgraded in severity, which is from the team coming up with ways to solve the issue. Other risks are no longer a problem, such as late delivery of the development boards as all have arrived.

The following item has increased its risk, and is currently being worked on

Risk Management, DDR

Risk Management, DDR

Design Review Materials

A link to the design review can be found here

A link to the pre-read can be found here

Plans for next phase

Detailed Design Gantt Chart

Detailed Design Gantt Chart

Individual Plans Three week plans created after the last design review are here, and are compared to what was completed. The three week plan for the next section are also included.

Steve Titus - 3 Week Plan, Preliminary Design Review - 3 Week Plan, Detailed Design Review

Ben Stewart - 3 Week Plan, Preliminary Design Review - 3 Week Plan, Detailed Design Review

Will McCaffrey - 3 Week Plan, Preliminary Design Review - 3 Week Plan, Detailed Design Review

Murali Prasad - 3 Week Plan, Preliminary Design Review - 3 Week Plan, Detailed Design Review

Jacob Allison - 3 Week Plan, Preliminary Design Review - 3 Week Plan, Detailed Design Review

Greg Malanga - 3 Week Plan, Preliminary Design Review - 3 Week Plan, Detailed Design Review


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