Integrated System Build & Test
Table of Contents
Team Vision for Integrated System Build & Test PhaseThe goal for this phase is for the team to complete testing on the populated boards and to find any issues with the current designs. These issues will be fixed in a second revision of the BMS. In conjunction with this, the boards were tested by the EVT firmware team to determine any issues, as well as creating the firmware required by the team. For this project the MSD team is responsible for creating validation firmware to show that the board is created correctly and can be programmed, then the EVT firmware team takes over.
The team was able to test the project and found several issues in terms of the electrical design of the project. This was budgeted for in terms of time, and a second revision with these issues fixed was send out to be ordered, as well as the remaining parts needed to populate the new boards. The master board, slave board and firmware portions of the project were subjected to more testing, as detailed below. Due to the amount of testing, the risk analysis for this phase has been updated. The team was able to show a small scale integration of the system, demonstrating progress being made before the April 15th Build Day for EVT when the system is attached to the motorcycle
Test Results Summary
Master Board Summary
The major hardware tests were performed on the master board in the previous phase. The major flaw found was the oscillator error. This was due to incorrect pin out on the board layout and has since been corrected. This was planned for in the original timeline, and can be seen in the gantt chart. Boards arrived Week 9, and then team began to populate and test the boards again. A similar amount of testing as seen in the previous phase has been performed.
The new test that has been completed on the master board is the "High Potential Test" which involves testing the board at high voltages for brief period of time. This allows for the team to confirm if the two ground planes are separate. This was proven, and seen in the test plan linked here
The remaining master test plans can be found here
Slave Board Summary
This phase, we were able to verify communications with the Slave board using the same Linduino test setup that we used last semester. This test fixture allowed us to test most of the primary functions of the LTC6811 without needing to write firmware for the microcontroller on the Master board.
The Slave 4.0 boards were tested using the cell simulations (with series resistor from Phase II), as well as with live lithium batteries. Detailed description of the tests are below.
As seen above, the QuikEval software read ADC values from the Slave board successfully. Values were confirmed with a multimeter. Values were consistently <0.5% off, which is well within our engineering requirements.
The same test was performed, but using live cells. Again, ADC readings were accurate to less than 10mV. Balancing of the cells was tested, and the Slave board worked as intended. We used an infrared thermal camera to get an idea of the temperature the board was reaching. See the figures below.
The power resistors on the Slave became very hot after only 10-15 seconds. This was more than expected, which cause motivation for a possible redesign for improved thermal performance (discussed below).
The Linduino & the LTC QuikEval software was not able to test complete functionality of the Slave board. The only remaining function left to be tested was GPIO output toggle for the temperature sense circuit MUX.
This phase, the EVT firmware team was able to open communications between the BMS Master and Slave board. The functions tested using this setup are:
- reading and writing configuration registers
- starting A-D conversions and polling
- reading cell voltages
To be tested are:
- ADC read from GPIO
- Digital output toggling of GPIO
These tests are expected to be complete during the last week of Phase 3.
Testing Results Summary:
- Manufacturing Tests (Complete)
- Continuity Tests (Complete)
- Isolation Tests (Complete)
- Regulator Testing (Complete)
- Initial Power on Test (Complete)
- Communications & Programmability Testing (Complete)
- Live Cell Testing (Complete)
- Full System Test (Partially complete)
- REV1 Final Evaulation Test (Incomplete, scheduled for 4/14).
Slave Redesign - rev 4.1
During testing, three issues were found on the 4.0 Slave board:
- The board in its current state is not able to be practically implemented on REV1. Should be able to be powered off 8 or 7 cells (Was not able to powered with 7). The problem was solved by adding a diode connecting te top of cell 7 to cell 8.
- isoSPI termination resistor was on the wrong side of th transformer T1.
- Balance resistors got very hot during discharge. Reached ~200°F after ~12-15 seconds of discharge. Larger copper pours were added to the power resistors to add thermal mass to sink the heat better. Instead of one large electrically-disconnected pad, there are several electricall-hot pads that will need to be covered by a thermal pad. If the Slave boards are mounted to the chassis and contact is made with this thermal pad, the chassis will act as a heatsink, drastically increasing thet cooling potential.
We decided to redesign the Slave board to resolve these issues, even though we would have been able to make everything work with the first revision. Boards were ordered early during the Spring break week to allow enough time to populate them for an integration test on REV1.
Slave 4.1 Assembly
A minimum of 4 boards with a preference of 10 need to be assembled and individually tested to hand off to EVT for an electronics and communication test fixture. As of 3/27/2018, 4 boards are populated. Spares are going to be made in the coming weeks.
The remaining Slave test plans can be found here
With the board populated from the previous phase, the major focus of this phase was to validate the firmware of the board. The following items were tested and confirmed to work.
As mentioned above the drivers for the IO layer responsible for base level interactions with devices external to the micro controller. The firmware team is now in the development and testing of the device layer. The device layer is responsible for controlling and communicating with all devices external to the micro controller. The most recent test is the LTC6811 device driver. The driver was able to correctly write and read from the chip's configuration register. Voltage readins were also able to be taken from the LTC on the slave board and and sent to the master board. This testing did reveal a hardware issue. When trying to control GPIO on the LTC6811 we discovered that the chip can only pull its output low. It is unable to drive the output high. We will have to make a minor hardware change to the boards to let the GPIO control the mux and LEDs.
This firmware validation allows the team to write software to the board, and create the "test software" to give to the customer. This software's purpose is to demonstrate the projects functionality. At this point, the EVT Firmware Team will take over future development of the board.
State of Charge
The small scale SOC test was done and all of the data was collected. The state of charge readings make sense with what was expected and the voltage readings are similar to normal lithium-ion voltage curves.
The remaining state of charge test plans can be foundhere
Risk and Problem TrackingIn this phase almost every major risk area was addressed.
- #6, Schematic Design Incorrect, Increased likelihood to 3, this was the issue found from the oscillator error on the masterboard. This risk has since been resolved in the second revision
- #8, Over Budget, increased in likelihood to 3. The team has gone over budget with the second revision. This is caused by the part ordering issue from Phases 1 and 2, as well as revisions to the BOM based on available parts. The customer was made aware of this, and due to the need of the project and the success so far, has granted the team additional funds.
- #20, Connectors don't satisfy requirements, Increased likelihood to 2. The MINI50-2 Connectors do not have keying versions in stock, with a lead time that is far beyond the end of our project, and a minimum buy of 4000. The team will use other methods of preventing cross connections.
The following risks have been found to be resolved and no longer pose a risk to the completion of the project.
Functional Demo Materials
For the demo, REV4.1 populated boards will be presented, with emphasis on showing the fixed issues. There will also be a software display showing the communications between the boards, and the progress of the software validation and checkout. The final timeline to customer implementation will be gone over.
The following is the poster draft
The following is a link to the team paper here
Testing Standards UsedAs part of the Advanced Circuits Sponsorship, the boards were designed based off the standards provided by Advanced Circuits to ensure functionality as well as reduce cost. This is accomplished by following the standards allowing the circuit cards to be produced easier.
Pikes Peak International Hill Climb has a number of electrical standards which our team will need to consider when developing our REV2 motorcycle. Of those, two specific standards are extremely relevant to our project. Relevant Competition Standards “All exposed conductors operating at greater than 36V must be properly insulated and marked with ‘High Voltage’ signs”. “A separate fuse (not a circuit breaker) will be placed in series with the main battery and the rating will not exceed 200% of the maximum expected current draw. All low voltage taps from the main battery will be separately fused. All fuses must be placed first in series with the battery starting at the positive connection”. The first can be mitigated with proper enclosure design, in addition to careful labeling in the harness and on the PCB. The second has been considered in the selection of individual fuses on all of the battery management system measurement points. These regulations are important for ensuring the safety of all competitors in the electric vehicle class. A full pdf of the 2017 competition rules can be found here: PDDR/PPIHC_Rulebook.pdf
Design Review Materials
A link to the design review can be found here
Plans for next phase
Individual Plans Three week plans created after the last design review are here, and are compared to what was completed. The three week plan for the next section are also included.