P18262: Battery Health Management System
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Preliminary Detailed Design

Table of Contents

Team Vision

Team 18262 plan for the preliminary design review is to create the schematic for the battery management board. In tandem with this the team plans on performing simulation and testing on all major subsections of the project and include the connectors, thermistors, state of charge, the microcontroller, hall-effect sensors and balancing array. All schematic designs will be created in the program “Altium Designer”, with the designs checked by subject matter experts, both at RIT and professionally.

The team was able to create the schematics for the board design and begin testing, which is documented on the preliminary design review. Multiple professional and academic subject matter experts reviewed the design. New risks were identified, and path of actions were put into place. Multiple parts were ordered that were deemed necessary for testing, and a complete BOM was created for the project. Overall the team was able to create the schematic design that best meets the customer requirements, and provide meaningful testing and simulation to back up assumptions and show feasibility.

Prototyping, Engineering Analysis, Simulation

Team 18262 engaged in significant prototyping of the circuit schematic. Work was done with a variety of tools. Linear Technologies “LTSpice” program was used to perform simulation on circuit sections to determine feasibility.

Sub-System Block Diagrams

Master Board
Master Board Block Diagram w/ Interconnects

Master Board Block Diagram w/ Interconnects

Slave Board
Slave Board Block Diagram w/ Interconnects

Slave Board Block Diagram w/ Interconnects

Thermistors

Two thermistors layouts were chosen to be simulated, one using a constant current source, and one using a reference resistor. A thermistor is a type of temperature sensor, and is basically a resistor whose resistance changes (almost) linearly over some temperature range. Post-processing with equations given in the part's datasheet can be used to determine the conversion.

By supply a constant current to the thermistor, the voltage changes as the temperature (and therefore resistance) changes. One way to build this is with a linear regulator, such as the LT317:

LT317 Constant Current Source Thermistor Measurement Simulation

LT317 Constant Current Source Thermistor Measurement Simulation

LT317 Constant Current Source Thermistor Measurement Simulation

LT317 Constant Current Source Thermistor Measurement Simulation

As you can see, we swept the thermistor resistance over its full range, but since it is a fairly high resistance, the regulator is not able to source this constant current very well for a high dynamic range.

Our chosen alternative is 3-wire thermistor measurement which uses a high-precision reference resistor to create a voltage divided with the thermistor, shown here. We swept the thermistor over its full practical range and were happy with the results.

3-Wire Thermistor Sense Circuit

3-Wire Thermistor Sense Circuit

We also swept the reference resistance to see which yielded the best results (the most linearity). A 15kohm reference resistor appeared to be the optimum value. The output is buffered for impedance matching with the ADC we are measuring the "vout" with.

Thermistor Sense Circuit Simulation

Thermistor Sense Circuit Simulation

Due to the electrical nature of the project, the team looked for outside mechanical advice. This focused on the mounting of the thermistors, and possible mechanical issues that could arise. Going forward this involves significantly more interface with the mechanical team. While the mechanical implementation of the thermistors is not within the scope of the project, knowing of possible issues before hardware implementation can allow the team to create a best implementation path. A full write up of the mechanical challenges can be seen here.

The major points looking forward are the following:

SOC

State of Charge Setup

State of Charge Setup

The hardware used in the test setup was the BQ34Z100EVM, an Arduino Uno, the Analog Discovery Module, a 4s battery pack, and a resistive load. The software used was the Arduino for communicating to the chip and the Waveform (analog discovery software) software for monitoring I2C communication.

Test Example

Test Example

This shows a test of communication by used one of the quick read commands and reading the internal temperature of the chip. The output of the read, 0x0B8F, is equivalent to 2959, which through the conversions given, is equivalent to 22.9°C and 73.22°F. This is about the temperature we would expect. This proves communication using I2C and can read from the chip.

MCU/Communications

The three major communication protocols to be utilized in this project are I2C, SPI, and CAN. The first step in determining the feasibility of each of these standards on the STMF3 platform was to gain a better understanding of the protocol itself. I2C and SPI are master – slave based communication protocols. In our case, a single master is used to communicate with one or more slaves. I2C is used to communicate between the master and the SoC chip. A typical I2C message structure is pictured below. The only connections between the master and the slave are a clock and data line. Part of the message structure is an address to be used to communicate to a specific slave on the bus.

I2C Protocol, (image credit Sparkfun.com)

I2C Protocol, (image credit Sparkfun.com)

Similarly, SPI uses a clock signal, two unidirectional communication lines, and a slave select line. This will be used to communicate with the slaves boards, after being transmitted as an ISOSPI signal.

Finally, controller area network, or CAN communication, is a bus based multi-master protocol. Isolated transceivers allow the battery management system to communicate with the larger vehicle network on the motorcycle over a differential signal, pictured below.

CAN Protocol

CAN Protocol

Balance Circuit Performance and Operation Conditions

One of the most important decisions regarding the balance circuit was the balancing current. This metric directly impacts balancing time, size, efficiency, and cost. See the calculations below:

Balance Circuit Calculations

Balance Circuit Calculations

3 hours is the Marginal value for our related engineering requirement. Using a balance current of 600mA is the perfect medium between size constraints and balance time.

SOC error is the percentage of allowable difference between cells. The value of 5% was taken to be the self-discharge of Li-ion cells after about 1 month.

Using this and the other cell characteristics, we calculated some worst case scenario metrics if we had to balance all but one cell:

Worst-Case Pack Loss Calculations

Worst-Case Pack Loss Calculations

Complete Balance Circuit Simulation

In order to verify functionality, connections and component choices, we ran many simulation of the balance circuit, in all sorts of conditions that we expect it to see. Several iterations were ran, with simple on/off balance currents (individual, overlapped, and simultaneous), as well as "fused" simulations.

Balance Circuit Simulation Model

Balance Circuit Simulation Model

Balanced Circuit Simple Switch, Individual

Balanced Circuit Simple Switch, Individual

Balanced Circuit Simple Switch, All ON

Balanced Circuit Simple Switch, All ON

Balanced Circuit Simple Switch, Offset

Balanced Circuit Simple Switch, Offset

To conserve space and cost, the balance circuit fuses were split between two balance circuits, allowing us to use half the amount of fuses. To ensure that this approach would work as expected, we simulated it with SPICE:

Balanced Circuit w/ Fuse Simulation

Balanced Circuit w/ Fuse Simulation

Slave Board Low-Voltage Supply Simulation

Because the Slave boards need to be always-on, efficiency is important to prevent significant pack discharge caused by large quiescent currents. The 5V supply on the slave board comes from the cells directly, using a switching DC/DC converter controlled by the Linear Technology LT3990. Pack discharge calculations were performed to determine how much energy we would lose in the pack given the sleep currents:

LV Supply Pack Loss Calculations

LV Supply Pack Loss Calculations

The LT3990 5V buck converter was also simulated in LTspice to observe some important characteristics, like step response and the sleep mode functionality:

LT3990 Transient Response, Pulsed EN

LT3990 Transient Response, Pulsed EN

LT3990 Transient Response, Pulsed EN

LT3990 Transient Response, Pulsed EN

LT3990 Transient Response: Rise Time and Overshoot

LT3990 Transient Response: Rise Time and Overshoot

Connectors

Connectors were chosen based off the criteria that there was not ability to cross connect the circuit, and that each connector is robust enough to handle many uses. For that reason, the Mini50 line is chosen. This is based off previous use of these connectors, which proved to be reliably, easy to use, and durable. These connectors are also mounted to the edge of the circuit board ensuring a strong connection. Four configurations are utilized, the Mini50-2,Mini50-4, Mini50-16 and Mini50-24. For connector sizes that are used more than once, different keying is used to ensure that the connectors are impossible to cross-wire.

Mini50-4 (Right) and Mini50-8 (Left)

Mini50-4 (Right) and Mini50-8 (Left)

Drawings, Schematics, Flow Charts, Simulations

Thermistors

 Requirements Traceability for Temperature Sensing

Requirements Traceability for Temperature Sensing

The thermistor setup uses all 4 GPIO pins and the ADC of the LTC6811. This allows significant cost savings, as the previous BMS board used a separate ADC on each chip. The signals are set to a multiplexer that selects a thermistor to be active. When active, the resistance across the thermistor is compared to the reference resistor, and sent through an amplifier to be read.

 Thermistor Setup

Thermistor Setup

MCU

Requirements Traceability for MCU

Requirements Traceability for MCU

The circuitry supporting the microcontroller focused on protecting the micro controller as well as ensuring proper function. The first and most important task is to make sure the microcontroller is powered correctly. This is done with a 5V to 3.3 voltage regulator. The 5V supply comes from the external low voltage sub system. A 0.5 volt fuse was placed on the 5V input to protect from any component failure shorts. A 3.6VZener diode was placed on the output of the 3.3V bus to protect the micro controller from over voltage.

 5V to 3.3V Voltage Regulator

5V to 3.3V Voltage Regulator

The microprocessor comes with an internal 8MHz clock. It has the ability to have an external 32MHz clock. The data sheet originally calls for a crystal to generate the clock signal. However, because this is a prototype a CMOS oscillator was selected instead. A zero-ohm resistor was placed between ground and the OSC_OUT pin because the datasheet was not descriptive. This allows us to experiment without ordering new boards.

 CMOS 32MHz Oscillator

CMOS 32MHz Oscillator

The microprocessor needs to communicate with the LTC6811s on the slave boards. An isolated twisted pair SPI chip is used. This IC converts four wire SPI into a twisted pair with galvanic isolation. This allows the boards to communicate despite having different ground references. Test points were also added for debugging SPI messages.
 Isolated SPI

Isolated SPI

Status LEDs were added for debugging and usability of the BMS. First a heartbeat LED was added to show that code is running on the microcontroller. Two sets of good, warning, and error LEDs have also been added. This is to indicate the current state of the BMS as well as the previous state. An example would be if the BMS went out of communication then came back, the present LED would be green, and the past would be yellow. This would indicate the BMS is good now but had an error state.

 Status LEDs

Status LEDs

A CAN bus is used to communicate with the rest of the bikes network. The CAN bus needs to be isolated for safety which also requires an isolated power supply. Test points were added for ease of debugging in this part of the design as well.

Isolated CAN

Isolated CAN

A JTAG interface is being used to program the micro controller. This is more robust programming method than using a UART system only, as well as offering more debug features.

 JTAG Interface

JTAG Interface

 MCU

MCU

State of Charge

Requirements Traceability for Hall Effect

Requirements Traceability for Hall Effect

State of Charge Schematic

State of Charge Schematic

This is the BQ34Z100 chip responsible for the State of Charge calculations. The I2C communication wires are on the right, going to the STM. The output from the hall effect is going into the sense resistor positive (SRP) terminal scaled to a maximum of 125 mV. The CE pin is a signal from the STM to turn on the chip for use. The BAT pin is where the output of the pack divided stack voltage circuit is fed in to.

State of Charge Current Sense Schematic

State of Charge Current Sense Schematic

This circuit scales the voltage output from the hall effect sensor for use in the SoC chip. It includes a mux to allow for switching between the high and low range of the hall effect sensor. The mux is operated through software.

State of Charge Voltage Sense Schematic

State of Charge Voltage Sense Schematic

The top chip takes the pack voltage and scales it down to provide the divided stack voltage at its output. The isolation chip has a gain of 8 and is used to isolate the two voltages and grounds. The bottom chip is an isolation from the Pack- and the LVSS ground.

Balancing

Requirements Traceability for Balancing

Requirements Traceability for Balancing

LTC6811-2: Balancing Control
LTC6811-2 Schematic

LTC6811-2 Schematic

5V Supply (LT3990) Schematic

5V Supply (LT3990) Schematic

Balance/Discharge Circuit

The following calculations were performed to determine power and size of the discharge resistors.

Balance Circuit Calculations

Balance Circuit Calculations

Full Balance Circuit

Full Balance Circuit

 Balance Circuit (zoomed in)

Balance Circuit (zoomed in)

Communications

In order to test the various communication protocols, a small amount of test code was required. For SPI and I2C, this simply involved using the default Mbed libraries and verifying that the output matched what was expected. CAN, however, required the use of two STM32F3 development boards communicating with one another. The flow chart below describes the basic setup of the test code.
CAN Protocol Test Code Flowchart

CAN Protocol Test Code Flowchart

This code, and some additional hardware to handle the differential signaling utilized by CAN, was utilized in the test setup. The figures below show the oscilloscope capture of an output message, along with the serial output from each MCU, verifying the success of the test.
CAN Protocol Oscilloscope Capture

CAN Protocol Oscilloscope Capture

CAN Protocol Test Serial Output

CAN Protocol Test Serial Output

Connectors

Connectors are split into the connectors on the slave board and those on the master board. The master board also contains all headers used for testing. These test points allow for easier debugging of the circuit.

For the Master Connectors, there is a Mini50-4 for the Pack Voltage In and Out. A four pin connector is chosen as the space between the pins will prevent shorts. For the slave connector both the cell voltage connector and the temperature sensor connector can be seen. The thermistors have one side connected to detect the voltage signal and the other side grounded.

Master Connectors

Master Connectors

Slave Connectors

Slave Connectors

Bill of Material (BOM)

The following image is the Bill of Materials. Important parts are the reference designation that correlate part with schematic placement. The parts are broken up into Master, Slave and Connectors to specify the specific part of the project that it is on. This is subject to change, but represents a snapshot of where the team is at currently.

Bill of Materials

Bill of Materials

The excel file can be seen here

Costs so Far

Costs so Far

Thanks to generous sponsorship, the team was able to save costs without having to purchase development boards. The costs for assembly are unknown as the team is not ready to get a quote from a PCB manufacturer, however it is expected to be within what is budgeted, based off market analysis. The costs for the slave and master are nearly complete, with slight changes based on iterations of the design in the next phase. The slave boards are closer to the worst case due to the connector choice. This is acceptable as the size for the connectors is vital to the project success.

Test Plans

The team used Test Plans to track the work done and the work planned to do. This allows for future replication of the project, as well as clear and precise methods for confirming that the requirements given are met.

Thermistors

The thermistor test plan can be seen here here

Thermistor Test Plan

Thermistor Test Plan

State of Charge

State of Charge Test Plan

State of Charge Test Plan

State of Charge Test Plan

State of Charge Test Plan

MCU/Communications

The communication test plan can be seen here

Communication Test Plan

Communication Test Plan

The MCU test plan can be seen here here

MCU Test Plan

MCU Test Plan

Risk Management

The first image contains all the risks found leading up to the preliminary design review, and the second image contains all the risks found in the preliminary design review. Mitigation plans for these risks are being created and will be tested in the detailed design review.

PDDR Risk After SDR Analysis

PDDR Risk After SDR Analysis

PDDR Risk After PDDR Analysis

PDDR Risk After PDDR Analysis

A list of all project risks can be found here.

Consideration of Relevant Standards

public/PDDR/ppihc.PNG

public/PDDR/ppihc.PNG

Pikes Peak International Hill Climb has a number of electrical standards which our team will need to consider when developing our REV2 motorcycle. Of those, two specific standards are extremely relevant to our project. Relevant Competition Standards “All exposed conductors operating at greater than 36V must be properly insulated and marked with ‘High Voltage’ signs”. “A separate fuse (not a circuit breaker) will be placed in series with the main battery and the rating will not exceed 200% of the maximum expected current draw. All low voltage taps from the main battery will be separately fused. All fuses must be placed first in series with the battery starting at the positive connection”. The first can be mitigated with proper enclosure design, in addition to careful labeling in the harness and on the PCB. The second has been considered in the selection of individual fuses on all of the battery management system measurement points. These regulations are important for ensuring the safety of all competitors in the electric vehicle class. A full pdf of the 2017 competition rules can be found here: PDDR/PPIHC_Rulebook.pdf

Design Review Materials

A link to the pre-read for the Preliminary Design Review can be found here A link to the Preliminary Design Review Presentation can be found here

Plans for next phase

Gantt Chart for Detailed Design Review

Gantt Chart for Detailed Design Review

Individual Plans Three week plans created after the last design review are here, and are compared to what was completed. The three week plan for the next section are also included.

Steve Titus - 3 Week Plan, System Design Review - 3 Week Plan, Preliminary Design Review

Ben Stewart - 3 Week Plan, System Design Review - 3 Week Plan, Preliminary Design Review

Will McCaffrey - 3 Week Plan, System Design Review - 3 Week Plan, Preliminary Design Review

Murali Prasad - 3 Week Plan, System Design Review - 3 Week Plan, Preliminary Design Review

Jacob Allison - 3 Week Plan, System Design Review - 3 Week Plan, Preliminary Design Review

Greg Malanga - 3 Week Plan, System Design Review - 3 Week Plan, Preliminary Design Review


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