P18262: Battery Health Management System
/public/

Subsystem Build & Test

Table of Contents

Team Vision for Subsystem Level Build & Test Phase

Team Plans for Subsystem Level Build & Test Phase

The team planned on populating and validating slave and master boards. This will allow the team to continue with testing of the boards, and allow the firmware team to begin testing on the boards. The surface mount lab (SMT Lab) in Building 78 will be used to do the majority of the population and validation. Any issues will be documented for the planned second spin of the BMS boards. The test plans on this edge page will be used to track the progress of the team.

Team Accomplishments for Subsystem Level Build & Test Phase

The team was able to populate the majority of each board. Several parts caused issues during testing, gone into more detail below. Overall the team was able to successfully validate the majority of the boards. The XRAY machine was used extensively in the SMT lab. Basic demos will be run during the design review to prove the functionality of the boards. The issues found are being added to the next revision of the board, which will be sent out to be ordered at the beginning of the next phase.

Test Results Summary

Test Plan Summary

Master Test Plans

A link to the most up to date master test plans can be found here

Work Accomplished

The boards were populated over the course of two weekends with all available parts. Only the U8, U5 and the oscillators have not been populated. The board has been put through the initial test plans, with detailed results seen here.

Initial Tests

Subsections Population (Completed Except for parts listed above)

* Oscillator (Failed Testing)

* CAN Isolation (In Progress)

Subsection Test (Not Started)

Full Function Test (Not Started)

Work to Be Completed

The oscillators have been found to be incorrectly designed on the project, with the pin out and footprint on the boards wrong. This was found during the 5V power on test. The board was consuming 700mA, significant over the current limit, and the voltage regulator was in thermal cutoff. Using EVT's Fluke Thermal camera it was quickly apparent that the oscillators were the cause of the issue as they were a higher temperature than every other chip, save the voltage regulator. The cause of this issue was Pin 3 on the oscillator Y1 connecting ground to the 3.3V output of the oscillator. The other oscillator, Y2, had a physical footprint larger than what was designed on the board, and was shorting the decoupling capacitor placed next to it. Once Y1 and Y2 were removed, the board consumed 70mA, which is what is expected.

The CAN isolation is ready to be tested once the 60 ohm 0603 capacitors arrive from DIGI-KEY. These were not ordered initially in December. This issue is rectified by placing the order through MSD PICS.

The Debugging LED D4 was damaged during population and needs to be fixed. This is a simple reheat and swap of the part.

High Potential testing will begin once the Pack In connector is installed on the board.

Images

Master Board in XRay Machine

Master Board in XRay Machine

Initail 5v Power on Test

Initail 5v Power on Test

Master Board Populated

Master Board Populated

XRAY Images

The team used the XRAY machine in the SMT lab to check all pinouts for correct soldering and to find any bridging before powering on the board. The following images were taken during this testing.

DC_DC Converter

DC_DC Converter

isoCAN

isoCAN

Oscillators

Oscillators

MOSFETs

MOSFETs

Transformer

Transformer

Voltage Regulator

Voltage Regulator

STM

STM

Scope Images of Sucessful Communications

Scope 1

Scope 1

Scope 2

Scope 2

Scope 3

Scope 3

Scope 4

Scope 4

Slave Test Plans

A link to the most up to date slave test plans can be found here

Work Accomplished

Two complete Slave boards were populated this phase. Testing was done in parallel with the assembly to catch any manufacturing errors and continuity errors faster. Both boards that were populated passed the criteria in the test plans. With the testing done so far, no issues have been found with the design.

No visual defects, all traces are intact

Continuity between all points is correct

Some parts were missing and manufacturing was incomplete.

Pins for certain test points are still missing, such as the GPIO and Mux output loops.

No solder bridging found

Random small blobs of solder not on the pads

None of these blobs are touching electrical points, and all blobs that could be removed were removed.

Both boards power on successfully when 32V is applied to Cell 12 TOS input.

The 5V supply works correctly.

Using the voltage divider, the voltage at all CELL_XX_IN from the top of cell #4 and above all equal TOS voltage (~32 Volts) for both slave boards. This will need to be investigated. Initial thoughts involve the diodes or MOSFETS.

Slave board B40S02 appears to be drawing excessive current through the regulator input resistor (R4?), dropping the voltage to ~3-4V from ~32V (with a 470 ohm resistor, that is about 500mA? There may be errors because it is unlikely that resistor is generating 15 watts of heat.

Populated Slave Boards (0x0 & 0x1)

Populated Slave Boards (0x0 & 0x1)

Multiplexer X-Ray

Multiplexer X-Ray

Voltage Regulator X-Ray

Voltage Regulator X-Ray

LTC6811 X-Ray

LTC6811 X-Ray

The Slave board was tested this phase in a similar fashion to how we did our concept validation tests with the LTC6811 development board. A string of resistors was built into the cell connector, and about 37V across the whole stack. This simulated having cells (about 3V across each cell input) without having to use live batteries. The configuration is shown here:

public/MSD2/Phase 2/cellsimharness.PNG

public/MSD2/Phase 2/cellsimharness.PNG

The LT3990 V+ to 5V regulator worked as expected. No issues were found with its operation. See the figure below.

Slave Board Power-ON Test 1

Slave Board Power-ON Test 1

Slave Board Power-ON Test2

Slave Board Power-ON Test2

This test was performed while the LTC6811 was not programmed. Individual cell discharge circuits were measured to check if all PMOS's were off (open), which they were. No unintended currents were flowing through the discharge resistors, which is what we wanted to see.

Work to be Completed

In Phase 3, we will begin the communications testing, beginning first with the LTC development boards, and then moving on to a system test with the Master Board.

Incorrect voltages at cell inputs using resistor divider.

This impacts LTC6811 voltage inputs.

Slave 02 regulator input (after resistor) not showing correct voltage.

Firmware Test Plans

Work Accomplished

Over the past few weeks firmware has been developed in a modular architecture to support the BMS as well as the rest of EVT’s boards with firmware needs. The architecture is shown below. We are developing on of STM’s mbed platform. This layer provides an easy to use hardware interface layer. In the past few weeks the firmware team has built the IO layer, responsible for all of the communication interfaces (UART, I2C, SPI, CAN). Current development is focused on the device layer. This layer contains classes facilitating the functions of all the chips and devices external to the microprocessor.

Firmware Architecture

Firmware Architecture

The IO layer being finishes has allowed us to test the communication lines on our boards. SPI has been tested. The oscilloscope/logic analyzer output can be seen below. The top line is SCLK, the next is MOSI, and finaly MISO. No slave was attached so there was no response. The second figure includes the waveform capture of the LTC6820 twisted pair ISO-SPI. GPIO was tested by blinking all of our LEDs. I2C and CAN are in the process of being tested.

Images

Test Logic Analyzer Output

Test Logic Analyzer Output

SPI Waveform

SPI Waveform

Risk and Problem Tracking

All identified hardware issues on the Master board have been identified within the issue tracking Trello board. The link below shows the current status of issue tracking, including successfully resolved issues and anything remaining. MSD2/Phase 2/P18262_ EVT BMS _ Trello.pdf

Risks Identified in Subsystem Build and Test Prep

The following risks have been identified or changed in severity

Issue with board wiring in battery box - New Risk, Risk entails the team being unable to connect all boards and cells to the BMS causing implementation issues. Meeting with Mechanical team to determine where and how the boards can be implemented.

Schematic Design Incorrect - Raised in likelihood due to the incorrect design of the oscillators on the master board. This is being fixed in the respin of the board (BMS 4.1)

Errors In fabrication - Raised in likelihood due to the bridging of D4 on the master board. Once this has been fixed, will decrease due to board XRAY tests showing the remained parts of the board have been designed correctly.

Late Delivery of Parts - Several last minute changed in MSD1 did not make it onto the BOM and therefore were not ordered. These parts have been identified and ordered.

Path Going Forward

All the risks identified in this phase have plans to completion, and should not impede process. The team is using an agile style of project flow, and have multiple groups working in tandem. The firmware is being developed alongside the population and validation of the boards. A second revision was accounted for in the team's Gantt chart.

Risk Table and Risk Over Phase Graph

Risk Changes MSD2 Phase 2

Risk Changes MSD2 Phase 2

Risk Table MSD2 Phase 2

Risk Table MSD2 Phase 2

Risk Graph MSD2 Phase 2

Risk Graph MSD2 Phase 2

This figure shows the decreasing risk importance, which is the sum of the importance column in the risk table. This allows the team to track how the risks change over the course of the project.

'''The excel file containing all risks can be found MSD2/Phase 2/Risk_Phase2.xlsx

Bill of Materials

A link to the BOM can be found here

Budget

The team has recieved 30 LTC6811 chips Linear Technology. This saves the team close to $300 on parts alone, and allows the team to stay within budget.

Budget

Budget

The remaining parts needed come in at around $270. This depends on what parts we can take from EVT and what parts get donated. A complete breakdown can be seen Remaining parts to Order

BMS Ledger to Date

BMS Ledger to Date

Testing Standards Used

As part of the Advanced Circuits Sponsorship, the boards were designed based off the standards provided by Advanced Circuits to ensure functionality as well as reduce cost. This is accomplished by following the standards allowing the circuit cards to be produced easier.
 Advanced Circuits Requirements for boards

Advanced Circuits Requirements for boards

public/PDDR/ppihc.PNG

public/PDDR/ppihc.PNG

Pikes Peak International Hill Climb has a number of electrical standards which our team will need to consider when developing our REV2 motorcycle. Of those, two specific standards are extremely relevant to our project. Relevant Competition Standards “All exposed conductors operating at greater than 36V must be properly insulated and marked with ‘High Voltage’ signs”. “A separate fuse (not a circuit breaker) will be placed in series with the main battery and the rating will not exceed 200% of the maximum expected current draw. All low voltage taps from the main battery will be separately fused. All fuses must be placed first in series with the battery starting at the positive connection”. The first can be mitigated with proper enclosure design, in addition to careful labeling in the harness and on the PCB. The second has been considered in the selection of individual fuses on all of the battery management system measurement points. These regulations are important for ensuring the safety of all competitors in the electric vehicle class. A full pdf of the 2017 competition rules can be found here: PDDR/PPIHC_Rulebook.pdf

Design Review Materials

A link to the design review can be found here

Plans for next phase

Subsystem Build and Test Gantt Chart

Subsystem Build and Test Gantt Chart

Integration Build and Test

Integration Build and Test

Individual Plans Three week plans created after the last design review are here, and are compared to what was completed. The three week plan for the next section are also included.

Steve Titus - 3 Week Plan, Subsystem Build and Test - 3 Week Plan, Integrated System Build and Test

Ben Stewart - 3 Week Plan, Subsystem Build and Test - 3 Week Plan, Integrated System Build and Test

Will McCaffrey - 3 Week Plan, Subsystem Build and Test - 3 Week Plan, Integrated System Build and Test

Murali Prasad - 3 Week Plan, Subsystem Build and Test - 3 Week Plan, Integrated System Build and Test

Jacob Allison - 3 Week Plan, Subsystem Build and Test - 3 Week Plan, Integrated System Build and Test

Greg Malanga - 3 Week Plan, Subsystem Build and Test - 3 Week Plan, Integrated System Build and Test


Home | Planning & Execution | Imagine RIT

Problem Definition | Systems Design | Preliminary Detailed Design | Detailed Design

Build & Test Prep | Subsystem Build & Test | Integrated System Build & Test | Customer Handoff & Final Project Documentation