Team VisionGoals for System Design Phase
Team 18262's plan for the System Design Phase and the SRD is to have a clear idea of the concepts and ideas the team can use for the project. These ideas are then combined into multiple concepts, and using Pugh Analysis and team discussion, a forward path is found.
The team was able to generate multiple design solutions, as well as test plans to determine using facts and numbers, what designs are actually the best going forward. As seen in the following EDGE page, MSD methods are used to back up the team's reasoning. The team leaves this phase with a strong idea of what needs to be done to achieve project success.
BenchmarkingPrevious MSD projects
Primary Issues with Previous BMS:
- Distributed architecture with multiple microcontrollers
- Excessively large
- Not fully utilizing BMS chip (LTC6802)
- Unreliable connectorization
- Limited processing power
- Max voltage limitation
Current Designs on Market
A functional decomposition chart is designed to help the team break down the project to different functions, and to explore in depth how they are related to each other.
Morphological ChartThe teams morphological chart expands in detail all different brainstormed solutions to the different sub-functions identified in the project. By looking at these sub-functions in detail, a multitude of different solutions can be created.
System DiagramGeneral BMS Block Diagram
The following image is the high level design of the battery management system.
Three different designs were discussed and broken out into a system level block diagram. These are the three main styles that will be considered. The strengths and weaknesses will be leveraged against the design and customer requirements.
Master Slave Series
Master Slave Parallel
Two major techniques exist when it come to cell balancing, active and passive. Both have major advantages and disadvantages, such as:
Active vs Passive Cell BalancingPassive
- Excess energy dissipated as heat
- Simpler, less efficient, typically cheaper
- Strong Cells support weaker cells
- More complex control scheme, more efficient, high footprint
Active Balancing Features
- Can transfer energy from one cell to another. - 2 Types of Active Balancing:
1. Capacitor based charge shuttling
2. Transformer based balancing
Capacitor Based Charge Shuttling
- Relatively new (Tesla released a Patent for this recently).
- Capacitors are connected to arrays of switches or relays to connect and disconnect the capacitors from nearby cells. The capacitor will be connected to 2 cells to a higher voltage. It will reconnect to one of those cells and discharge its contents into that cell.
- This would require a large number of transistors.
- Those transistors would need to be electrically isolated.
- There are losses as current is passed through the transistors and capacitors.
- Charge needs to be shuttled up and down the whole stack.
- This could possible cheaper than transformer based balancing because there are no transformers.
- Cells not being balanced are still involved in shuttling charge up and down the stack.
- This may have a limited current carrying capability depending on capacitor size, resistances, and switching frequency.
Transformer Based Cell Balancing
- Each cell has a transformer and 2 FET's, 1 on the cell side, and another on the common side.
- Every cell can be individually controlled for Charge/Discharge/Off states.
- Working examples can be found.
- Transformers isolate the cells from each other and from the common voltage bus across the whole stack.
- Transformer balancing can work at fairly high currents (>2.5 amps).
Advantages of Active
- A single cell with less capacity will discharge faster than other cells. Passive balancing will drag all cells down to the level of the weakest cell.
- A bad cell would ruin the whole pack, the whole pack would have to stop discharging to avoid damaging the lowest cell. This would lead to under-utilized battery capacity.
- Active balancing solves this issue by taking a small amount of charge from all the stronger cell and transferring it to the weakest cell.
- Active balancing would also allow a cell with a higher voltage than the others to be discharged.
- Balancing a single weak cell is extremely costly in terms of wasted energy with passive, but not with active.
- Balancing an over charged cell is mildly costly with passive, and minimally costly with active.
- Many monitoring chips have low current passive balancing built-in.
Disadvantages of Active
- Active balancing is generally expensive and complicated. Estimates are that a system for actively balancing 100 cells in series could cost $350-400 and upwards of $500 to build.
- Transformers create magnetic fields which could interfere with nearby electrical components.
- The size will generally be large.
- For many chips, a separate voltage monitoring chip is needed.
Passive Balancing Features- Measures cell voltages and discharges the cells with higher voltage until they are down to the same voltage level as the others.
- Can be used with an internal chip, or with a resistor array and external FET's.
Internal Chip Balancing
- The BMS chip can carry a small amount of current.
- Power can be dissipated through the chip or through a small resistor.
-This approach would be extremely compact and cheap.
- Balance current would be limited and cannot be scaled.
- Risk: The chip would be directly connected to the cell with little to no buffer. This poses the possibility of voltage spikes damaging the chip.
Resistor Array Balancing
- The BMS chip reads cell voltages, but is used to control external MOSFETS capable of higher current.
- Power is dissipated through a bank of resistors. More resistors can be added to dissipate more power.
- This uses more space and is more expensive than internal, but is far cheaper than active balancing.
- EVT has existing examples using resistor arrays.
Advantages of Passive Cell Balancing
- Passive balancing is fairly cheap and much simpler than active balancing.
- Passive balancing is more reliable because it only used resistors and an ON/OFF state of the FET's.
- A resistor bank scales well for different discharge currents.
- Balancing algorithms would be fairly simple.
One of the primary considerations when deciding whether to use active or passive balancing is the required balancing current. For currents of about 1A and higher, it makes more sense to use active balancing. Conversely, with currents of around 100mA and lower it makes more sense for passive.
Below are some simple calculations to determine minimum required cell balancing current based on our engineering requirement for a balance time of around 2 hours.
Calculations were performed using Mathcad. The complete document with all these calculations can be found here.
The math therefore suggests that a balance current of 100mA will facilitate a complete pack balance in 1.5 hours, well under the required time. While not a definitive cause for ruling out active balancing, this analysis did provide significant attraction towards a passive BMS design.
Design IdeasSix different designs were identified as possibilities. Two designs, D and E, take a different approach than the others. Design D aims to build the most simple BMS board to meet the requirements, and design E aims to create a BMS if cost was not an issue. Design F is the previous BMS system, version 3.3, which is used as a datum for comparing the other five designs. These best and worse case scenarios allow the team to dive into what are the real key functions of the project. This also allows the team to have an exercise in "What if" and explore all concepts. All six designs are then subjected to a Pugh Analysis to determine the best concept.
The Pugh Analysis table allows all six designs to be examined against each other and against the requirements, to decide which design meets the customer requirements the best. The complete spreadsheet containing all the requirements information can be found here.
The full Pugh Analysis can be found here:here.
Pugh Analysis for State of Charge (SoC)
Reasoning for Rankings
There were a few methods for calculating state of charge. Coulomb counting came out as the best choice because it is very accurate. There are also multiple ways to implement it including a dedicated chip or writing our own algorithm. It does cost more than some other options but that was not as important as the other factors. Depending on how it is implemented, the sizing would differ but will still be small. Since current sensing will already be part of the BMS, coulomb counting is very feasible.
Pugh Analysis for Chip Selection
Battery management chip selection is arguably one of the most important aspects of the overall design, as the feature set of each of the chips we evaluated was slightly different. That being said, the LTC6811 was the clear winner, beating if not tying the alternatives in every category. To start, the proprietary ISO-SPI interface allows for one of the fastest measurement speeds evaluated and tied for the highest precision cell voltage measurement. While the number of temperature sensor inputs aren't quite enough to meet our requirements, the auxiliary pins can be configured as an I2C or SPI interface, which will allow us to expand our analog input count. Finally, and perhaps most importantly, the LTC6811 is a direct upgrade from the LTC6802 chip used on the last version of the EVT BMS. This, in combination with our industry connections at linear technologies, will allow us to implement the chip more quickly and effectively than any of the other options. Additionally, we have the potential to get these chips donated by our industry contacts, potentially saving us hundreds of dollars in components. Given the importance of the system, however, we were careful to choose a secondary BMS chip, in the event that we discover the LTC6811 will not be suitable for this project. The MAX14920, while slower and less feature rich, is solid runner-up to our current selection. We will continue evaluating the two chips simultaneously until we reach a point where we deem the LTC6811 sufficient.
Pugh Analysis for Communication Architecture
Reasoning for Rankings
The BMS 3.3 currently uses a parallel split harness. The process of enumerating the bus currently has to be hard coded into each BMS. The options to fixing this are using a series daisy chain or parallel bus configuration. A series configuration would make the enumeration process easy but adds in a single point of failure which is unacceptable. The number of wires can be minimized by moving to a shared harness. A parallel configuration with a shared harness is the best choice.
Pugh Analysis for Active vs Passive Balancing
Reasoning for Rankings
Passive balancing was selected as the method of balancing the batteries. Both Active and Passive balancing met the customer and engineering requirements, the cost of active, as seen in the following cost analysis, proved to be the deciding factor.
Pugh Analysis for Temperature Sensing
From the Temperature Sensor Pugh Analysis, the thermistor was decided to be the best solution. The low cost compared to the resistance temperature detector (RTD) at $0.50 per thermistor vs $3.00 for the RTD gave the strongest argument to use the thermistor. While both the RTD and thermistor provided accurate measurements for a small size, due to the number of cells in this design, the cost cannot be overlooked. The RTD did have better temperature compensation, which is the accuracy of the measurements, both the thermistor and RTD fit the engineering requirements for this. The small size of the thermistor made it a more optimal solution to the thermal diode, which while a similar cost, takes up a significantly larger space. From a bench-marking perspective, a thermistor has been used in previous designs, and is considered a solid option to use.
Pugh Analysis for Safety
Reasoning for Rankings
Safety systems are broken up into two categories: environmental/protection, and emergency pack cutoff.
Environmental/protection refers to safety on the boards themselves. Pugh anaylsis was performed for several possible solutions, but there it was determined that multiple solutions would be best.
One of the problems that existed for BMS 3.3 was overcurrent situations in the balance circuit. A simple and inexpensive solution is fusing the balance circuits. Conformal coating is a insulating spray-on coating, which will help prevent foreign object faults and internal short circuits. In addition, insulated and keyed connectors will prevent user error when connecting the system together. These four solutions were chosen because they are cheap and easy to implement but also would have a major impact on system safety.
Pack cutoff solutions exist to prevent catastrophic failures on the motorcycle by cutting power to the motor controller. Solutions considered were existing contactor control (indirect and direct), additional independent contactor, transistors, and pack fusing. Contactors already will be mounted on the bike, so in the case of an emergency, the BMS will be able to signal to the Gateway to cut power. Fuses on the input to the motor controller will prevent sustained overcurrent conditions.
Pugh Analysis for Processors
Reasoning for Rankings
The BMS 3.3 used a 16 bit pic microcontroller that was difficult to use, limited on power and memory, and became a limiting factor on the last revision of the BMS. The selection process for a new microproccessor focused on fixing these issues. A requirement of the STM32F3 family was the starting point. The family is broken up into branches, each focusing on different features. The final choice STM32F302C8 was in the USB and CAN branch. Communications on a CAN bus is a requirement. There were other processors in the branch. Some in the performance branch had more than enough memory but became unmanufacturable for us with 144 pin packages. Some 64 pin options were available aswell but with the added complexity of manufacturing compared with the PIC's 32 pins, and a higher cost, those were also eliminated. The STM32F302C8 gives the BMS 64 KB of flash, multiple communication channels for expandability on future revisions, while being in a manageable 48 pin package.
Pugh Analysis for Thermal Management
Reasoning for Rankings
The PCB Thermal Relief came out as the best choice for many reasons. One being that it can keep the BMS cool enough for the requirements. Another is that it doesn’t add much extra size compared to the other options. It is also very feasible since it was used on the previous iteration of the BMS and is known to work.
Pugh Analysis for Current Sense
Two viable solutions emerged from the current sense Pugh analysis: Dual range hall-effect and chassis mount shunt. Some feasibility testing was performed for more detailed analysis.
Current Sense Feasibility
To help guide our design choice with regard to current sensing, we executed our current sense test plan. This involved bench testing on REV1 and comparing data acquired by both methods (hall effect and shunt).
The above figure shows all data on separate plots. The top left was taken with EVT's USB oscilloscope, used as a baseline for measurement accuracy. The current shunt stands out to be very noisy, with random spikes. This is, of course, undesirable. The bottom graphs show the two outputs of the dual-range hall-effect sensor.
The figure below shows all the signals on one plot.
All the above data was acquired with an Arduino. To eliminate possible error from a fairly low resolution ADC, the output of the hall-effect was also monitored with the oscilloscope, shown here:
As seen in the lower plot, the difference (error) of the hall-effect sensor typically stays below 5A. The only time it goes above 5A is during current spikes, which are out of range for the low-current output channel of the sensor. The hall-effect we used has another high-current output channel, not used in the second run. Therefore, the hall-effect sensor we used meets our marginal values detailed in the engineering requirements.
All relevant files, including raw test data, Arduino code and MATLAB scripts are in this zip file here.
Concept Selection and Feasibility
Based off the bench-marking and Pugh Analysis the following design was deemed to be the best.
Design A was chosen based off the cost and complexity. The passive balancing combined with the two chips selected, allows the board to meet the customer needs as well as staying within budget. The two chips will be tested in parallel to determine the best fit, as both were found to suit the requirements from the Pugh Analysis. This will help mitigate risk by allowing both chips to be tested to confirm that they can meet the requirements. The multi channel hall effect for current sensing is selected due to the different states that the electric motorcycle will be in. There is a large difference in battery usage between the motorcycle racing on the track, versus moving the bike to and from the track.
Test plans were generated to compare the requirements and the concept selection to determine compliance.
Test Plan Summary
- Test shunt and hall-effect on REV1, compare performance metrics.
- Use Arduino for data collection. Use USB oscilloscope for baseline measurements.
- Explore concerns with hall-effect vs. shunt
Test Plan Summary
- Connect to a setup using the 50V pack
- Use a current shunt for current input to chip
- Use Picoscope as a baseline for current measurements
- Have Arduino for communication and data collection
Test Plan Summary
- Verify communication between LTC6811/LTC6820 and Arduino (microcontroller)
- Prevent/expose potential firmware-related blocking issues early on.
- Verify cell voltage and temperature sensor reading by LTC6811 dev board. Read this data using the Arduino.
Severity is ranked as
- Not ideal, but manageable
- Damage to system and motorcycle
- Catastrophic failure
Probability is ranked as
- 0% to 25% chance of happening
- 25% to 75% chance of happening
- 75% to 100% chance of happening
The complete risk assessment table can be found here.
System Design Review
The pre read for the System Design Review can be found here
The System Design Review presentation can be found here
Three Week Plan
Gantt Chart The Gantt Chart for team progress, and work outline can be found at this link: Gantt Chart for System Design and Forward
Individual Plans Three week plans created after the last design review are here, and are compared to what was completed. The three week plan for the next section are also included.3 Week Plan 9/14/17 to 10/12/17 - 3 Week Plan 10/12/17 to PRD