P18342: IEEE Design Challenge




Stage 1 public/Chris_Stage1.png

The first stage in the design is a LT1615 charge pump used to step up the constant 1 V to 3.3 V. This 3.3 V is used to bias the Op Amps in the later stages.

Stage 2 public/Chris_Stage2.png The second stage is made up of 9 Op Amps. One of the Op Amps is used to produce a constant 0.25 V. The 0.25 V is then successively subtracted from the variable input voltage 3 times to produce V5, V3, and V7. The variable input voltage is subtracted from the constant .25 V to produce V2, V4, V6, and V8. The Op Amps that produce V1 - V8 have their negative supply grounded so the outputs stay at 0 V until needed. V1 - V8 are shown in the figure below.


The last Op Amp is used to produce a constant 0.85 V. This voltage is used as the gate voltage of the NMOS Transistors of the next stage.

Stage 3 public/Chris_Stage3.png

The last stage forms the sinusoidal output. The gate voltage of each transistor was chosen to ensure the transistor will enter the saturation region at around 0.125 V. Using the drain voltages produced by Stage 2, the sums of the current of each side of the circuit will resemble rectified sinusoids that are 90 degrees out of phase. Taking the final output as the differential of these wave forms will produce the desired sinusoidal output.




Bill of Materials

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